Referso Jobs

FPGA Electrical Engineer III

BLUE ORIGIN · Posted Nov 9, 2026

Open

Altadena, California, United States
On-site
Full-time · Senior
$131K–$183K per year
5+ years

FPGA Electrical Engineer III

BLUE ORIGIN · Posted Nov 9, 2026

Open

Altadena, California, United States
On-site
Full-time · Senior
$131K–$183K per year
5+ years

Staff Design Engineer - SoC & RTL

Lattice Semiconductor · Posted Sep 11, 2026

Open

Pune, Maharashtra, India
On-site
Full-time · Senior
6+ years

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Full‑time SoC RTL Design Engineer focused on FPGA projects in Pune, India.

Responsibilities

Serve as a key contributor to FPGA design efforts
Drive logic design of key FPGA blocks & full chip
Ensure design quality through assertions, checkers, and scripting
Develop strong relationships with worldwide teams
Mentor and develop strong partners and colleagues

Requirements

BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent
Nice to have: Familiarity with FPGA designs, use‑cases, and design considerations

Skills

RTL design Verilog System Verilog SoC integration micro‑architecture definition ARM processor AXI AMBA bus

SOC RTL Design Engineer

Lattice Semiconductor · Posted Jul 17, 2026

Open

Pune, Maharashtra, India
On-site
Full-time · Mid
6+ years

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SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration.

Responsibilities

Serve as a key contributor to FPGA design efforts
Drive logic design of key FPGA blocks & full chip
Ensure design quality through assertions, checkers, and scripting
Develop strong relationships with worldwide teams
Mentor and develop strong partners and colleagues

Requirements

BS/MS/PhD Electronics Engineering, Electrical Engineering, Computer Science or equivalent
Nice to have: Familiarity with FPGA designs, use-cases, and design considerations
Nice to have: Experience selecting 3rd party IP

Skills

RTL design Verilog System Verilog SoC integration micro-architecture definition ARM processor AXI

SOC RTL Design Engineer

Lattice Semiconductor · Posted Oct 21, 2026

Open

Pune, Maharashtra, India
Full-time
6+ years

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SoC RTL Design Engineer focused on FPGA projects in Pune, India.

Responsibilities

Serve as a key contributor to FPGA design efforts
Drive logic design of key FPGA blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality
Ensuring design quality through assertions, checkers, and scripting
Develop strong relationships with worldwide teams
Mentor and develop strong partners and colleagues

Requirements

BS/MS/PhD Electronics Engineering
BS/MS/PhD Electrical Engineering
BS/MS/PhD Computer Science

Skills

RTL design Verilog System Verilog SoC integration Micro-architecture definition 3rd party IP selection ARM processor

SRAM Compiler Circuit Designer

Apple · Posted Nov 7, 2026

Open

Munich, Bavaria, Germany
On-site
Senior

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Senior Circuit Designer within our Digital Design Engineering group, responsible for developing innovative ASICs and leading SRAM compiler IP requirements.

Responsibilities

Drive the development of SRAM, register files, and latch arrays to enable high-performance, low-power design.
Lead the SRAM compiler IP requirements for foundry, vendors, and internal IP teams.
Understand the complete design flow spectrum, including DFT and testing aspects of compiler IPs, and integrate them into our SOCs.
Collaborate with logic/architecture teams to capture specifications of SRAM, register files, and latch arrays, driving their implementation.

Requirements

Bachelor’s in Electrical Engineering (BSEE)
Nice to have: Masters/PhD in Electrical Engineering
Nice to have: tape-out of high-performance, low-power circuit design
Nice to have: ML-based programming algorithms
Nice to have: automation solutions for rapid and dynamic design

Skills

circuit design memory arrays SRAM design register file design

Functional Safety Architect

NXP Semiconductors · Posted Nov 6, 2026

Open

Austin, Texas, United States
3+ years

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Deliver state of the art functional safety Platform and IP solutions to Automotive and Industrial products compliant with ISO 26262 and IEC 61508.

Responsibilities

Deliver state of the art functional safety Platform and IP solutions to Automotive and Industrial products compliant with ISO 26262 and IEC 61508.
Define safety requirements for Platform and IP modules.
Support the management of Platform and IP modules developed as SEooC through its entire lifecycle, working in close collaboration with internal Design Teams.
Prepare the safety modules for functional safety assessment.
Support SoC integration of safety Platform and IP including implementation of IP assumptions of use.

Requirements

Bachelor's in Electronics Engineering
Bachelor's in Computer Engineering
Master's in Electronics Engineering
Master's in Computer Engineering

Skills

ISO 26262 IEC 61508 FMEDA FTA DFA fault injection

IP Integration Engineer

Inabia Software & Consulting Inc. · Posted Nov 7, 2026

Open

Remote, United States
Remote
5–7 years

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IP Integration Engineer

Responsibilities

Good in understanding RTL Design and Digital concepts
Subsystem or SoC integration
Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.
SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration
Ensure customer satisfaction

Requirements

4 year degree
advanced degree

Skills

RTL Design Digital concepts SoC integration IP integration verilog system verilog synthesis timing constraints

FPGA Engineer (Senior-Level)

Maania Consultancy Services · Posted Nov 5, 2026

Open

Houston, Texas, United States
On-site
Full-time · Senior

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Responsibilities

Complete pre-employment background check and drug screening
Hands-on FPGA development
Integrate FPGA designs into system-wide hardware/software environments
Apply embedded C/C++ knowledge for SoC integration and bus protocols (UART, SPI, I2C, I2S)
Deliver high-quality VHDL modules and verification environments

Requirements

Bachelor of Science in Electrical Engineering

Skills

FPGA development Embedded C/C++SoC integration UART SPI I2C I2S VHDL Verification environments Test benches

Senior Director Analog & Mixed Signal (AMS) Engineering

MaxLinear, Inc. · Posted Nov 5, 2026

Open

Bangalore, Karnataka, India
Senior
15+ years

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Lead and scale the AMS engineering organization in Bangalore, providing strategic and functional leadership across analog and digital design, systems engineering, layout, validation, and product execution, while overseeing the Taiwan Applications Engineering team.

Responsibilities

Lead multidisciplinary engineering teams across Analog, Digital, Layout, Systems Engineering, and Validation functions
Provide functional leadership for the Taiwan Applications Engineering team and ensure alignment with product, marketing, field, and customer requirements
Own the complete product development lifecycle, from architecture and design through validation, qualification, production release, and sustaining support
Drive integration of analog, mixed‑signal, and digital technologies, including embedded control, calibration, interfaces, telemetry, and firmware interactions
Establish strong systems engineering practices to translate market and customer requirements into product specifications, architecture decisions, and verification plans

Requirements

BS/MS in Electrical Engineering, Computer Engineering, or a related field; advanced degree preferred
Nice to have: interface connectivity
Nice to have: serial transceivers
Nice to have: bridges
Nice to have: isolators

Skills

analog and mixed‑signal IC development

RTL Design & Integration Engineer

Inabia Software & Consulting Inc. · Posted Nov 4, 2026

Open

Remote
Remote
5–7 years

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RTL Design & Integration Engineer

Responsibilities

Good in understanding RTL Design and Digital concepts
Subsystem or SoC integration
Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.
SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration.
Ensure customer satisfaction.

Requirements

4 year degree
advanced degree

Skills

RTL Design Digital concepts SoC integration Verilog SystemVerilog synthesis timing constraints floor-planning

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