Lead design verification and design engineering for subsystems in Microsoft’s cloud hardware.
Compensation
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Technically lead a subsystem as a design or DV engineer
Collaborate across teams on vertical and horizontal reuse of components
Provide technical leadership through mentorship and strong teamwork
Work effectively with Architecture, Design, DV, PD, DFT, firmware, and post-silicon teams to debug system-level issues and deliver silicon from concept through bring-up
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: Experience debugging RTL designs
Nice to have: Experience with design quality and static checks
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Collaborate on executing the block level place and route assignments from Netlist through GDS flow
Interact with design team to solve problems and propose physical design engineering ideas
Coordinate all timing budgeting required for physical design task with respective teams
Close STA timing across all corners and modes for blocks and generate ECO independently
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
Collaborate on executing the block level place and route assignments from Netlist through GDS flow.
Interact with design team with purpose to solve problems and propose physical design engineering ideas.
Coordinate all timing budgeting required for physical design task with respective teams.
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently.
Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM. Execute block level place and route assignments from Netlist through GDS flow. Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed. Close STA timing across all corners and modes for blocks and should be able to generate ECO independently. Work with design teams for closing CTS, IO timing, DFT timing. Responsible for digital design automation, flow-automation and regression across RTL-to-GDSII.
Responsibilities
Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Execute block level place and route assignments from Netlist through GDS flow
Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently
Work with design teams for closing CTS, IO timing, DFT timing
Engineer responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM, executing block level place and route assignments from Netlist through GDS flow.
Responsibilities
Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Execute block level place and route assignments from Netlist through GDS flow
Interact with design team to solve problems and propose physical design engineering ideas
Coordinate all timing budgeting required for physical design task with respective teams
Close STA timing across all corners and modes for blocks and generate ECO independently
Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Engineer will be responsible for working with teams on executing the block level place and route assignments from Netlist through GDS flow
Interacting with design team with purpose to solve problems and propose physical design engineering ideas
To Coordinate all timing budgeting required for physical design task with respective teams
To close STA timing across all corners and modes for blocks and should be able to generate ECO independently
Engineer will be responsible for working with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM
Engineer will be responsible for executing the block level place and route assignments from Netlist through GDS flow
Interacting with design team to solve problems and propose physical design engineering ideas
Coordinate all timing budgeting required for physical design task with respective teams
Close STA timing across all corners and modes for blocks and generate ECO independently
Responsible for designing and implementing FPGA solutions for networking and security products, turning system-level requirements into functional, high-performance FPGA designs.
Responsibilities
Design and implement FPGA logic based on system-level requirements
Develop and maintain block diagrams, constraints, and pin mappings
The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead the architecture and design of complex CPU subsystems for next‑generation high‑performance networking switch ASICs
Use expertise in all stages of ASIC development from specification and RTL design through post‑silicon bring‑up
Collaborate closely with SDK, board‑support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms
Requirements
Bachelor's degree
Master's degree
PhD
Nice to have: Leading CPU/SoC subsystem architecture
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