You will play a critical role in ensuring our products meet all architectural specifications and functional requirements.
Responsibilities
Executes functional validation plans and test suites at system and subsystem levels under a variety of operating conditions.
Acts as the first line of defense for system failures by isolating, reproducing, and debugging complex functional, performance, and power-related issues.
Performs deep-dive root cause analysis to determine whether failures originate from hardware, software, firmware, or test environment issues.
Develops and maintains automation scripts and tools (Python, LabView, etc.) to streamline test execution, data collection, and CI flows.
Collaborates cross-functionally with Hardware/ASIC Design, Firmware, Architecture, and Software teams to communicate findings, propose workarounds, and verify fixes.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field (or equivalent experience)
Nice to have: CI pipelines
Nice to have: automated validation frameworks
Nice to have: experience working in highly cross-functional, global engineering teams
Lead the architecture, development, integration, validation, and lifecycle support of next-generation AI server, storage, networking, and rack-scale infrastructure platforms.
Locations (2)
Austin, Texas, United States
Texas, United States
Compensation
The salary range for this position is $182k - $236k.
Responsibilities
Lead the architecture, development, integration, validation, and lifecycle support of next-generation AI server, storage, networking, and rack-scale infrastructure platforms
Serve as the technical authority for PCI Express, Memory, Power Delivery, and Systems Management technologies across the complete product lifecycle
Drive platform innovation, quality, reliability, and performance while partnering with silicon vendors, ODMs, manufacturing, quality, firmware, systems engineering, and hyperscale customers
Lead critical technical investigations, root-cause analysis, and field escalations
Provide strategic technical leadership across multiple engineering organizations
Lead the design and architecture of integrated SoC and connectivity solutions across silicon, firmware, software drivers, and hardware integration for data center, industrial, and embedded platforms.
Compensation
MaxLinear's good faith estimate starting base salary range is: $164,000 to $231,000 Annually
Responsibilities
Drive end‑to‑end systems definition across silicon architecture, firmware, software drivers, and hardware integration
Define and own systems level architecture for SoC, connectivity, and interface products
Lead architectural decisions across hardware/firmware partitioning, bus fabric and system integration, performance, latency, power, security, and scalability trade offs
Define platform level management, security, and telemetry capabilities
Partner with Product Management on product definition, roadmap planning, competitive and system level differentiation
Entry-level Graduate Electrical Engineer supporting design, development, testing, and validation of electronic solutions within HP’s Large Format Printing organization.
Responsibilities
Support the design and development of electrical and electronic solutions, including components, subsystems, integrated circuitry, and algorithms.
Participate in testing and validation of electronic designs covering functionality, reliability, electromagnetic compatibility, thermal performance, safety, and power measurements.
Contribute to the development of reliable, cost-effective, and high-quality hardware solutions for HP products.
Work closely with experienced electrical engineers and multidisciplinary teams throughout product development stages.
Collaborate with internal teams and external development partners in an international engineering environment.
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Telecommunications Engineering, Physics, or a related technical field
Define the Micro-architecture of the CPU hardware. Develop the CPU hardware using a Hardware-Description-Language. Perform functional debug and closure of the design. Responsible for timing and power closure of the design for the target Frequency and Power. Prepare documentation of the Design Specification. Design and develop hardware for Apple's mobile devices. Evaluate new ideas and features for the Central Processing Unit (CPU) hardware.
Compensation
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,294 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Responsibilities
Define the Micro-architecture of the CPU hardware
Develop the CPU hardware using a Hardware-Description-Language
Perform functional debug and closure of the design
Responsible for timing and power closure of the design for the target Frequency and Power
Prepare documentation of the Design Specification
Requirements
Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field
Developing and maintaining SystemC/TLM-based performance models for next-generation AI silicon products to enable architecture exploration, scalability analysis, and performance projection.
Responsibilities
Develop, maintain, and enhance SystemC/TLM-based performance models representing critical AI silicon subsystems.
Drive modeling of key architectural components including SoC fabrics, on-chip communication networks, memory controllers, and scale-up/scale-out fabrics.
Implement new architectural features and capabilities based on evolving product requirements.
Improve model fidelity, scalability, maintainability, and simulation performance.
Perform detailed debugging and root-cause analysis of model issues and performance anomalies.
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