- Pune, Maharashtra, India
- Full-time · Senior
- 12+ years
Responsibilities
- Serve as a key contributor to FPGA design efforts
- Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area
- Ensuring design quality through all physical design quality checks and signoff
- Develop strong relationships with worldwide teams
- Mentor and develop strong partners and colleagues
Requirements
- BS in Electronics Engineering
- MS in Electronics Engineering
- PhD in Electronics Engineering
- BS in Electrical Engineering
- MS in Electrical Engineering