Develop, maintain, and enhance CAD methodologies and automation flows supporting digital ASIC design, verification and implementation.
Compensation
The US hourly range for this full-time position is $25.80 to $47.80.
Responsibilities
Develop, maintain, and enhance CAD methodologies and automation flows supporting digital ASIC design, verification and implementation.
Work with industry-standard EDA tools across formal verification, synthesis, static timing analysis, power analysis to improve design quality, productivity, and flow efficiency.
Develop Python, Tcl, and shell-based scripts and utilities to automate design workflows, analyze results, and streamline engineering processes.
Explore and develop AI-assisted solutions to address practical challenges in CAD and semiconductor design workflows.
Investigate and deploy applications of large language models (LLMs), retrieval-augmented generation (RAG), and AI agents for engineering automation and intelligent workflow assistance.
Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and silicon validation across multiple sites to deliver advanced connectivity silicon products.
Senior technical leader in DTCO to define and drive co-optimization of Intel Foundry's next-generation process technologies for analog, mixed-signal, and custom design.
Locations (2)
Hillsboro, Oregon, United States
Santa Clara, California, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
Responsibilities
Lead AMS DTCO for future Intel Foundry nodes: evaluate device architecture, front-end and back-end design rules, metal stack, and patterning choices against analog, mixed-signal, and custom-design requirements.
Run a closed-loop DTCO process: sense issues from designers, partners, and test chips; prioritize by PPA and productivity impact; drive rule, PDK, or flow changes; and validate the result on silicon and in design.
Quantify technology impact on circuits through layout studies, parasitic-aware benchmarking, and area and performance scaling analysis of representative AMS building blocks.
Expected Base Pay Range (USD) 242,080 - 362,600, $ per annum
Responsibilities
Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and silicon validation across sites including Irvine, Santa Clara, Ottawa, Pavia, Aachen, Bucharest, Vietnam, and India
Own end-to-end execution of one or more major product families — from RTL design through tape-out, bringup, and production release
Drive first-silicon success across next-generation 200G/lane and beyond connectivity products on 3nm and 2nm process nodes
Establish and continuously improve design flows, verification methodologies, DFT strategies, and emulation infrastructure to accelerate delivery and quality
Partner with architecture, systems, and product management teams to define the technical roadmap for next-generation connectivity products
Requirements
BS/MS/PhD in Electrical Engineering, Computer Engineering, or related field
Define and drive design-rule and PDK requirements with process, design-rule, OPC, and quality and reliability teams, including high-voltage device support, density and fill rules, metal width and spacing options, and layout-dependent effects.
Partner with EDA vendors on node enablement for custom and AMS flows: custom layout, analog placement and routing, physical verification, fill, and extraction; translate tool and flow feedback into technology decisions.
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