Own and maintain the internal design backend API and qubit design framework, develop new parametric components, extend export pipeline, build automation layer, support internal users.
Compensation
Our success is your success: own it with our BSPCE plan
Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.
Responsibilities
Own and maintain the internal design backend API and qubit design framework: code quality, testing, CI, releases, documentation
Develop new parametric components and layout primitives with the chip designers who use them
Extend and harden the export pipeline to electromagnetic and circuit simulation tools
Build the automation layer for large-scale, hierarchical chip layouts in close partnership with our physical-design and scale-up engineers
Support internal users: onboarding, debugging, API design, and turning recurring pain points into features
Mid-level Process Engineer role focused on semiconductor microfabrication to develop and manufacture critical parts of the localized electrodeposition process.
Responsibilities
Follow, maintain and develop process flows for the fabrication of Syenta’s LEM stamps
Take ownership of assigned process modules from definition through to stable, repeatable execution
Characterise and optimise unit processes (e.g., lithography, deposition, etch, plating)
Execute structured experiments and data analysis to improve yield, uniformity and throughput
Document processes clearly through run sheets, SOPs and technical reports
Requirements
Bachelor’s degree or equivalent in Nanotechnology, Electrical Engineering, Mechanical Engineering, Physics, Chemistry, Materials Science, or related field
Lead the receiver (Rx) photonic integrated circuit for the OPU platform, owning design from photodetector device to chip-level architecture and tapeout.
Locations (2)
Austin, Texas, United States
Sunnyvale, California, United States
Responsibilities
Define the Rx PIC architecture, including optical input coupling, routing, demultiplexing, and layout of dense photodetector arrays
Design and optimize high-speed photodetectors for responsivity, dark current, capacitance, bandwidth, linearity, and saturation
Model the device and receiver with optical, electrical, and RF simulation
Work with the electronic IC team on the PD–TIA interface
Analyze array-level effects such as optical and electrical crosstalk, uniformity, thermal behavior, and yield
Requirements
PhD in Electrical Engineering, Applied Physics, or Physics
Nice to have: 5+ years of experience developing high-speed silicon photonics receivers or photodetectors
Lead the development of high-speed modulators that move data into the optical domain on the OPU platform, owning modulator design from concept through tapeout.
Locations (2)
Austin, Texas, United States
Sunnyvale, California, United States
Responsibilities
Lead high-speed silicon photonics development, focusing on high-speed modulators (e.g., carrier-depletion Mach-Zehnder, micro-ring/micro-disk, and traveling-wave designs).
Design and optimize modulators for EO bandwidth, VπL, insertion loss, extinction ratio, and energy per bit, using optical, electrical, and RF co-simulation.
Lead layout and tapeout of photonic test vehicles and product blocks in foundry PDKs, including DRC/LVS sign-off and design-for-test structures.
Define RF electrode, termination, and driver-interface requirements together with the electronic IC and packaging teams.
Support wafer- and die-level testing (small-signal EO S-parameters, eye diagrams, BER, DC/thermal tuning), and correlate measured results with models to improve the next design.
Lead process integration for advanced semiconductor and photonic devices, enabling next-generation high-performance interconnect technologies
Compensation
$147,000.00 - $202,500.00
Responsibilities
Lead process integration for advanced semiconductor and photonic devices
Translate device architectures and design layouts into robust, manufacturable process flows across development and pilot manufacturing
Drive C&F activities, including rapid proof-of-concept and prototyping builds
Define and track critical process parameters and integration metrics; partner with module owners to optimize unit processes
Own end-to-end integration flow execution, including process definition, build scheduling, risk assessment, and readiness
Requirements
Ph.D. in Electrical Engineering, Materials Science, Physics, or related discipline (Master’s degree with relevant industry experience will be considered)
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