Advanced packaging technology development engineer focused on silicon photonic packaging and electronic-photonic integration.
Compensation
The starting salary range posted for this position is $154,900.00 to $225,300.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Drive definition, design and analysis of packaging technology test vehicles
Drive validation of new technology against key performance metrics
Apply deep process expertise to oversee wafer processing, fine pitch bumping, D2W/W2W hybrid bonding, fanout, advanced substrate development, and assembly
Work with top-tier foundry and assembly partners to develop and qualify robust packaging solutions for high density photonics integration, CPO and on-board optics
Utilize design and modeling experience to guide Design for Manufacturability (DfM) and Design for Reliability (DfR)
Requirements
PhD or MS in Mechanical Engineering, Electrical Engineering, Physics, or a related field
Own and maintain the internal design backend API and qubit design framework, develop new parametric components, extend export pipeline, build automation layer, support internal users.
Compensation
Our success is your success: own it with our BSPCE plan
Direct IP Compensation: Earn substantial bonuses for driving the core patents that define our quantum architecture.
Responsibilities
Own and maintain the internal design backend API and qubit design framework: code quality, testing, CI, releases, documentation
Develop new parametric components and layout primitives with the chip designers who use them
Extend and harden the export pipeline to electromagnetic and circuit simulation tools
Build the automation layer for large-scale, hierarchical chip layouts in close partnership with our physical-design and scale-up engineers
Support internal users: onboarding, debugging, API design, and turning recurring pain points into features
Mid-level Process Engineer role focused on semiconductor microfabrication to develop and manufacture critical parts of the localized electrodeposition process.
Responsibilities
Follow, maintain and develop process flows for the fabrication of Syenta’s LEM stamps
Take ownership of assigned process modules from definition through to stable, repeatable execution
Characterise and optimise unit processes (e.g., lithography, deposition, etch, plating)
Execute structured experiments and data analysis to improve yield, uniformity and throughput
Document processes clearly through run sheets, SOPs and technical reports
Requirements
Bachelor’s degree or equivalent in Nanotechnology, Electrical Engineering, Mechanical Engineering, Physics, Chemistry, Materials Science, or related field
Lead the receiver (Rx) photonic integrated circuit for the OPU platform, owning design from photodetector device to chip-level architecture and tapeout.
Locations (2)
Austin, Texas, United States
Sunnyvale, California, United States
Responsibilities
Define the Rx PIC architecture, including optical input coupling, routing, demultiplexing, and layout of dense photodetector arrays
Design and optimize high-speed photodetectors for responsivity, dark current, capacitance, bandwidth, linearity, and saturation
Model the device and receiver with optical, electrical, and RF simulation
Work with the electronic IC team on the PD–TIA interface
Analyze array-level effects such as optical and electrical crosstalk, uniformity, thermal behavior, and yield
Requirements
PhD in Electrical Engineering, Applied Physics, or Physics
Nice to have: 5+ years of experience developing high-speed silicon photonics receivers or photodetectors
Lead the development of high‑speed silicon photonics modulators for the OPU platform, owning design from concept through tapeout and collaborating with test and packaging teams.
Locations (2)
Austin, Texas, United States
Sunnyvale, California, United States
Responsibilities
Lead high‑speed silicon photonics development
Design and optimize modulators for EO bandwidth, VπL, insertion loss, extinction ratio, and energy per bit
Lead layout and tapeout of photonic test vehicles and product blocks in foundry PDKs
Define RF electrode, termination, and driver‑interface requirements
Support wafer‑ and die‑level testing and correlate results with models
Requirements
PhD in Electrical Engineering, Applied Physics, or Physics
Nice to have: 5+ years of experience in high‑speed silicon photonics
Nice to have: full design‑to‑tapeout‑to‑fabrication‑to‑testing cycle
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