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Own end-to-end talent acquisition for Lattice Semiconductor's engineering organization, focusing on niche semiconductor talent in India and expanding to US and global markets.

Responsibilities

Own end-to-end recruiting from sourcing through offer close for niche FPGA/semiconductor talent
Build and execute proactive deep sourcing strategies for niche technical talent
Source passive candidates through unconventional channels
Partner closely with local India hiring managers to build full end-to-end recruiting ownership
Track hiring metrics and provide data-driven insights on market dynamics

Requirements

Master's degree in HR, Business, or Engineering-related field
Nice to have: hardcore sourcing experience across North America, APAC, and India
Nice to have: startup or high-growth product company experience
Nice to have: building talent pipelines in competitive semiconductor markets

Skills

AI/ML recruiting tools Boolean search X-ray search headhunting passive candidate sourcing

Senior Staff Design Engineer

Lattice Semiconductor · Posted Aug 28, 2026

Open

Penang, Malaysia
Senior
15+ years

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Lead the development, integration, and productization of high-performance interface solutions for FPGA products.

Responsibilities

Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interface subsystems.
Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP.

Requirements

Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
Nice to have: multiple interface families (PCIe, Ethernet, USB, MIPI CSI-2/DSI, D-PHY/C-PHY, SerDes)
Nice to have: PHY and mixed-signal behavior
Nice to have: clocking
Nice to have: calibration

Skills

RTL design subsystem integration

SOC RTL Design Engineer

Lattice Semiconductor · Posted Jul 17, 2026

Open

Pune, Maharashtra, India
Full-time
6+ years

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SoC RTL Design Engineer to join the HW design team focused on IP design and full chip integration.

Responsibilities

Serve as a key contributor to FPGA design efforts
Drive logic design of key FPGA blocks & full chip
Ensure design quality through assertions, checkers, and scripting
Develop strong relationships with worldwide teams
Mentor and develop strong partners and colleagues

Requirements

BS/MS/PhD Electronics Engineering
BS/MS/PhD Electrical Engineering
BS/MS/PhD Computer Science

Skills

RTL design Verilog System Verilog SoC integration micro-architecture definition ARM processor AXI AMBA bus ENET

SOC RTL Design Engineer

Lattice Semiconductor · Posted Oct 21, 2026

Open

Pune, Maharashtra, India
Full-time
6+ years

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SoC RTL Design Engineer focused on FPGA projects in Pune, India.

Responsibilities

Serve as a key contributor to FPGA design efforts
Drive logic design of key FPGA blocks & full chip and bring best-in-class methodologies to accelerate design time and improve design quality
Ensuring design quality through assertions, checkers, and scripting
Develop strong relationships with worldwide teams
Mentor and develop strong partners and colleagues

Requirements

BS/MS/PhD Electronics Engineering
BS/MS/PhD Electrical Engineering
BS/MS/PhD Computer Science

Skills

RTL design Verilog System Verilog SoC integration Micro-architecture definition 3rd party IP selection ARM processor

Senior Engineer (Level 1)

Arrow Electronics, Inc. · Posted Feb 27, 2025

Open

Noida, Uttar Pradesh, India
On-site
Full-time · Senior
5–20 years

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Senior Engineer focused on RTL design, Lower Power Synthesis, and UPF Flow with ASIC/FPGA experience.

Responsibilities

RTL design
Lower Power Synthesis
Low Power Design
UPF Flow
RTL debug

Skills

RTL design Verilog VHDL ASIC FPGA Lint/CDC tool Xilinx Altera/Intel FPGA I2C SPI UART PCIe MIPI AXI

Engineer - FPGA

Arrow Electronics, Inc. · Posted Oct 3, 2024

Open

Pune, Maharashtra, India
Full-time

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Responsibilities

Responsible for design and development of FPGA RTL with Verilog/VHDL
Analyse domain specific technical or low level requirement and modification as per end customer or system requirement
Participate in high level requirements analysis, High level and low level RTL design
Perform testing including unit and functional testing
Troubleshoots FPGA design problems which are complex in nature

Skills

Verilog VHDL RTL design unit testing functional testing troubleshooting

See full job description

Sr. ASIC Design Engineer

Hewlett Packard Enterprise · Posted Nov 8, 2026

Open

Sunnyvale, California, United States
Hybrid
Full-time · Senior
$159K–$321K per year
5+ years

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As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist for routers and switches.

Compensation

United States of America: Annual Salary USD 158,500 - 321,000 in California

Responsibilities

Produce a detailed micro-architecture specification from a functional specification of a module that meets power/area requirements
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs
Work with the Physical Design team for optimal floorplan and timing closure
Identify and fix timing in RTL to meet the frequency target

Requirements

Bachelor’s degree in Electrical Engineering
Master’s degree
Nice to have: Computer Architecture
Nice to have: networking protocols
Nice to have: s/lint

Skills

Verilog System Verilog RTL design Functional coverage SVA

General Support Engineer – Aerospace, Defense & Government (ADG)

Altera · Posted Jul 9, 2026

Open

Portsmouth, New Hampshire, United States
Full-time · Mid
$96K–$139K per year
3+ years

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Provide hands‑on technical support for FPGA‑based board and system platforms in aerospace, defense, and government applications.

Compensation

$96.0K - $138.9K USD

Responsibilities

Provide board‑ and system‑level support for FPGA‑based platforms used in ADG applications
Perform hardware bring‑up, validation, and debug in lab and customer environments
Troubleshoot complex issues related to signal integrity, power integrity, and system integration
Support high‑speed interfaces (e.g., DDR, PCIe, Ethernet) and resolve performance issues
Collaborate with FPGA, hardware design, and software teams to diagnose and resolve system‑level challenges

Requirements

Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field
Nice to have: aerospace
Nice to have: defense
Nice to have: government programs
Nice to have: Altera FPGA platforms

Skills

hardware bring‑up lab debug troubleshooting FPGA‑based systems

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