Senior ASIC/FPGA Engineer to join the Applied Research and Technology (ART) Microelectronics Technology team, contributing to the development of cutting-edge defense solutions across Mission Systems, leveraging expertise in the design, implementation, verification, and integration of high-performance digital FPGAs & ASICs.
Compensation
The salary range for this role is 86,800 USD - 165,200 USD.
Responsibilities
Capture requirements, ASIC / FPGA digital architecture and design using RTL, timing closure, verification, and system integration
Optimize FPGA implementations to meet performance, power, and size constraints
Collaborate with cross-functional teams to integrate ASIC/FPGA solutions into larger systems
Follow all applicable development processes, procedures, and guidelines
Participate in Agile team meetings and planning activities
Requirements
Degree in Science, Technology, Engineering or Mathematics (STEM)
Nice to have: High-speed digital interfaces and protocols (DDR, PCIe, Ethernet)
Lead and develop a global Design Verification organization, define and execute a reuse-first verification strategy spanning SystemC models, RTL, IP, subsystems, SoCs, and Virtual Platforms.
Responsibilities
Define and drive the verification strategy for SystemC models, RTL designs, reusable IP, subsystems, SoCs, and Virtual Platforms.
Lead and develop a global Design Verification organization, including verification leads, engineers, external partners, and project-specific teams.
Establish a common verification architecture that supports reuse of test intent, stimulus, sequences, checkers, scoreboards, assertions, coverage models, and regression infrastructure across SystemC and RTL.
Develop scalable SystemVerilog/UVM environments, including protocol adapters and TLM bridges that connect pin-level UVM interfaces to SystemC/TLM models.
Establish functional-equivalence and timing-correlation methodologies between SystemC LT/AT models and RTL implementations.
Requirements
Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
Google's software engineers develop the next‑generation technologies that change how billions of users connect, explore, and interact with information and one another.
Participate in, or lead design reviews with peers and stakeholders to decide amongst available technologies.
Review code developed by other developers and provide feedback to ensure best practices (e.g., style guidelines, checking code in, accuracy, testability, and efficiency).
Triage product or system issues and debug/track/resolve by analyzing the sources of issues and the impact on hardware, network, or service operations and quality.
Contribute to existing documentation or educational content and adapt content based on product/program updates and user feedback.
Requirements
Bachelor’s degree or equivalent practical experience.
Master's degree or PhD in Computer Science, or related technical fields.
Develop logic design, RTL coding, and simulation for SoC designs, contributing to the design and development of next-generation technologies that power the future of computing.
Responsibilities
Develop logic design, RTL coding, and simulation for SoC designs
Define and implement architecture and microarchitecture features for logic blocks
Perform quality checks across RTL, timing, power, and design integrity to meet performance goals
Optimize RTL logic to ensure compliance with power, performance, area, and timing targets
Collaborate with IP providers to integrate and validate IPs at the SoC level
Annual base salary ranges:
· FPGA Engineer, Level I: $125,000–$160,000
· FPGA Engineer, Level II: $145,000–$195,000
· Sr. FPGA Engineer, Level III: $160,000-$215,000
Your level and base salary will be determined individually based on job-related knowledge, skills, education, and experience.
In addition to base salary, you may be eligible for company stock, stock options, or long-term cash awards; discretionary bonuses; and the opportunity to purchase additional stock at a discount through an Employee Stock Purchase Plan.
Responsibilities
Develop highly reliable FPGA firmware for Sovera hardware.
Work across engineering disciplines to bring new products from prototype through production and flight.
Own your firmware throughout its lifecycle, including verification testing, documentation, and support.
Apply rigorous development and verification practices to deliver reliable firmware for spaceflight.
Collaborate with avionics, software, and platform engineers to design, integrate, and validate FPGA implementations.
Requirements
Bachelor's degree in computer science, electrical engineering, mathematics, or another engineering discipline; or at least two years of professional software development experience in place of a degree.
As Senior DFT Engineer, you'll own DFT implementation end-to-end: defining the DFT micro-architecture for our accelerators, developing and integrating it into internal RTL and third-party IP, driving implementation with our backend design partner, and ensuring high-quality silicon bring-up through comprehensive pre-silicon validation.
Compensation
The base salary range for this role is $200,000 – $300,000.
Responsibilities
Micro-architect and implement DFT instrumentation logic, including scan insertion, compression, ATPG, memory BIST, boundary scan (IEEE 1149.x), IJTAG (IEEE 1687) infrastructure, and debug/observability features.
Integrate DFT IP into internally developed RTL, and evaluate and integrate DFT capabilities from third-party IP providers.
Work directly in RTL, synthesis, and DFT tool flows.
Develop comprehensive DFT verification plans and validate DFT functionality through simulation and gate-level verification.
Drive stuck-at, transition, cell-aware, and power-aware ATPG strategies, ensuring DFx coverage targets are achieved before tapeout.
Requirements
BS, MS, or PhD in Electrical Engineering or Computer Engineering
Lead design and verification of next‑generation Switch Silicon chips for NVIDIA’s Networking business unit.
Responsibilities
Work in a design/verification team developing core units within the Switch silicon
Plan micro‑architecture of dynamic verification environments for units and modules
Design dynamic verification environments for units/blocks according to specifications under challenging constraints with high orientation to power, area, and performance
Collaborate closely with Architecture, u‑arch, Full chip Micro‑Architecture, BE, and FW teams
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