Lead the DCGPU Quality Diagnostics team, which owns debug and failure analysis for AMD Data Center GPU products across the production lifecycle, from silicon screening through System rack assembly. This people-leadership role covers product quality, factory yield and board-level failure analysis.
Responsibilities
Hire, lead and develop a team of quality and diagnostics engineers
Set the team's initiative roadmap, priorities and resources to support product launches and production ramps
Own the quality escalation process for DCGPU production failures, from triage through root cause, corrective action and closure
Define and track the team's key metrics, failure paretos, test escapes, time to root cause and how much diagnostic coverage has improved
Lead the work of feeding failure analysis results back into diagnostic coverage, so failures move to earlier test stages
Define how engineers and software teams observe and diagnose multi-die computing systems, owning run-control, trace, performance counters, and post-mortem capture from architecture definition through silicon bring-up.
Responsibilities
Own the SoC debug and trace specification, including run-control access, a common trace record format, and observability requirements for bring-up, performance diagnosis, and failure analysis.
Define secure JTAG and run-control behavior for compute engines, cores, management controllers, and other relevant subsystems, including halt and step capabilities.
Specify instruction, compute-engine, microcontroller, fabric-transaction, die-to-die, and network-gateway trace sources.
Architect trace funnels, cross-die triggers, on-chip buffers, and a synchronized package-wide time base aligned with RAS error records.
Define trace capture and export paths, including optional spill to memory and readout over PCIe; set bandwidth limits and measure the effect of tracing on workloads.
Requirements
Bachelor’s degree in Electrical Engineering
Bachelor’s degree in Computer Engineering
Bachelor’s degree in Computer Science
Nice to have: Trace synchronization across multiple dies
Lead the strategy and development of ultra-low-power, low-noise analog/mixed-signal ASICs for next-generation implantable neural interface technologies.
Compensation
Salary Range: $225k - $275k
Responsibilities
Define and own the ASIC technology strategy and multi-generation roadmap
Build, lead, and develop an internal ASIC design and verification team
Own ASIC program schedules, budgets, resource plans, and tape-out milestones
Serve as Synchron's senior ASIC technical authority and report status and risks to executive leadership
Partner with systems, electrical, firmware, quality, regulatory, and clinical leaders to align ASICs with product needs
Requirements
Bachelor's degree in Electrical Engineering, Microelectronics, or a related field
Nice to have: Master's degree or Ph.D. in Electrical Engineering
Nice to have: building an ASIC team from an early stage
Nice to have: ultra-low-power design for implantable or wearable medical devices
Lead design and technology support for advanced HBM DRAM products, bridging internal teams, foundries, and technology groups to translate process capabilities into scalable, high‑performance architectures.
Compensation
$150,000.00 - $308,000.00 a year
Responsibilities
Provide critical technology support for design and development of advanced HBM DRAM products
Serve as a bridge between internal design teams, foundries, and technology development groups
Translate advanced process capabilities into scalable, high‑performance architectures
Support design and deployment of AI‑enabled solutions that improve efficiency and decision‑making
Define resilience across multi-die computing systems, translating reliability targets into hardware, firmware, and software requirements for fault detection, error containment, recovery, and telemetry.
Responsibilities
Own the end-to-end RAS specification, reliability and availability targets, FIT budget by domain, common error records and timestamps, and software-visible error-bank mapping
Define fault detection, correction, logging, and diagnosis across compute engines and cores, caches, HBM and LPDDR memory, die-to-die and scale-up links, PCIe/CXL, and management agents
Specify ECC, parity, residue checks, memory scrubbing, retirement or repair, and in-field screening to prevent and detect silent data corruption
Define end-to-end poison propagation, containment, retry, and recovery for correctable and uncorrectable errors
Specify isolation, fencing, and degraded-operation behavior for compute units, cores or clusters, memory resources, links, and package-level failures
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field
Nice to have: Processor error-reporting architectures
Design and optimize high-performance analog and mixed-signal ICs for automotive and industrial applications, including transistor-level design, simulation, silicon validation, and product qualification.
Responsibilities
Design and optimize analog and mixed-signal circuit blocks such as amplifiers, voltage references, regulators, data converters, and sensor interfaces.
Perform transistor-level design, simulation, and verification across process, voltage, temperature, and reliability conditions.
Drive silicon bring-up, characterization, debugging, and root-cause analysis through technically sound closure.
Contribute to product robustness, yield improvement, and long-term reliability.
Collaborate closely with Layout, Verification, Product, Test, and System Engineering teams.
Requirements
Bachelor's in Electrical Engineering, Microelectronics, Physics, or a related field
Master's in Electrical Engineering, Microelectronics, Physics, or a related field
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