Lead design and implementation of advanced semiconductor package technologies for Microsoft’s cloud infrastructure.
Compensation
Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Own 2.5D/3D package designs for Azure datacenter silicon
Develop package architecture and floorplans using CoWoS and HBM integration
Drive package and PCB co-design and optimization
Do package layout and routing in EDA tools
Run package design signoff and drive closure before tapeout
Requirements
Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: Master’s Degree with 15 years of experience in semiconductor package product development
Nice to have: 10+ years hands-on experience in Semiconductor Package design, development, manufacturing, supplier management or quality management
Lead design and development of custom silicon IP for Microsoft’s Azure Cobalt chips, collaborating across architecture, firmware, verification, and physical design teams to deliver high‑performance, power‑efficient RTL and FPGA solutions.
Locations (2)
Redmond, Washington, United States
United States
Compensation
Silicon Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Own and lead FPGA design environment efforts for rapid IP prototyping and design validation including root‑cause analysis of complex system issues.
Own development of custom IP RTL from microarchitecture through RTL implementation, verification, and post‑silicon validation.
Collaborate with architecture, SoC, firmware, verification, and physical design teams to deliver high‑quality FPGA and IP solutions.
Develop high‑performance, power‑efficient RTL designs and drive PPA optimization across the design lifecycle.
Define and document the microarchitecture for digital designs within the TPU
Partner with Verification to develop test plans and debug RTL, and collaborate with Physical Design to achieve timing, area, power, and manufacturability goals
Drive critical power optimization and automation initiatives across all on-chip-network components and subsystems
Support post-silicon validation and hardware debugging efforts to ensure successful deployment
Lead the development and enhancement of internal design tools, flows, and engineering methodologies
ASIC Design Engineer, Cloud TPUGoogle · Sunnyvale, US