STA & Timing Closure Engineer to lead static timing analysis and signoff execution for high-complexity, multi-GHz System-on-Chip (SoC) architectures on advanced FinFET and GAA nodes (5nm, 3nm, 2nm).
Compensation
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
Responsibilities
Architect, configure, and maintain rigorous STA environments across hundreds of process, voltage, temperature (PVT), and operational modes
Develop, audit, constraints for complex clock structures
Collaborate closely with physical design teams to analyze timing bottlenecks; generate precise ECOs—both automated and functional/manual
Validate timing margins against foundry standard cell, macro, and interface IP characterization data
Run strict signoff audits to guarantee zero critical timing violations prior to tapeout
Senior engineer responsible for synthesis, static timing analysis, and timing constraint development within Nordic Semiconductor’s Short‑Range Product Development Group.
Locations (2)
Trondheim, Trøndelag, Norway
Oslo, Oslo, Norway
Compensation
Competitive salary with short- and long-term incentive plan
Responsibilities
Develop, improve, and validate timing constraints for accurate implementation and timing analysis.
Synthesize RTL into gate‑level netlists, optimizing performance, power, and area to meet project requirements.
Analyze and resolve timing issues using STA across operating conditions and process corners.
Achieve timing closure by implementing and assessing engineering change orders (ECOs) to meet performance and schedule targets.
Partner with digital design and architecture teams to translate design intent into implementation and provide guidance on functional, performance, and timing goals.
Assist in Cadence Innovus/Tempus (Back-End & signoff Design Tool) regular regression review and develop/maintain testsuites to ensure the good STA quatlity.
SerDes Applications engineer for ASIC Product Division (APD). Work as part of a team of highly skilled applications engineers providing first class support to customers from pre-sales to product deployment.
Compensation
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00
Responsibilities
Validation of SerDes performance on test silicon with setup and external channel(s) representing customer application
Working with SI and SerDes development team to resolve any performance marginality observed
Testing evaluation boards with test silicon, documentation of the hardware and software for deployment at customer site
Development of software/scripts to enable customers to be able to run large number of loops with voltage, temperature margining over different configurations and channels
Support customer queries related to configuration of the SerDes, initialization sequence, API, reference clock requirement, power noise specifications
Provide technical expertise, support and guidance for research and teaching activities in the Characterisation Facility in the School of Metallurgy and Materials.
Compensation
Full time starting salary is normally in the range £30,062 to £31,900, with potential progression once in post to £35,883
Responsibilities
Train and support facility users with materialography and heat treatment laboratories
Run samples for external and internal customers
Repair and care for equipment
Prepare equipment for use through routine maintenance and calibration
Replenish and restock consumables
Requirements
Degree in materials science, engineering, physical science or similar
Nice to have: Materialographic sample preparation (metallography, ceramography or plastography)
Nice to have: Optical or electron microscopy techniques
As a CPU Circuit Design Engineer, you will play a pivotal role in shaping the performance of Intel's cutting-edge CPUs. You will design, simulate, and optimize circuits to achieve the best trade-offs between speed, power, area, and reliability, ensuring that our products meet stringent quality and schedule demands.
Compensation
Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD
Responsibilities
Drives performance verification (PV) methodology and circuit / timing quality signoff for the CPU team
Evaluates new process nodes through circuit simulations and/or block scaling methods, recommends frequency targets for the CPU with an early understanding of u-architectural growth
Makes informed trade-offs between performance, power, area, and effort
Works with design domains RTL/circuit/SD to converge to timing targets with no compromise on quality or schedule
Own pre-to-post silicon VF correlation and drive debug of circuit marginality sightings
Validates and researches compiler optimizations, partial reconfiguration flow, and debugging features for Altera FPGA hardware.
Responsibilities
Validates and researches compiler optimizations, partial reconfiguration flow, and debugging features like SignalTap & System Console using Quartus Design Software and Altera FPGA hardware
Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA hardware boards
Regresses designs during each release for QoR and monitors performance over targeted FPGA devkits
Collaborates with cross-functional teams to develop and improve validation strategies and resolve customer issues
Requirements
Master's/Bachelor's Degree in Electronics/VLSI/Digital Design or other related disciplines
Senior Synthesis and STA EngineerNewNordic Semiconductor · Trondheim, Norway+1 more
Senior Facility Technician (Characterisation)University of Birmingham · Birmingham, United Kingdom
NPU STA/Timing Engineer (Lead/Staff/ Sr Staff)Qualcomm · Bangalore, India