Marvell is seeking a visionary Associate Vice President (AVP), Engineering to lead a critical engineering function within the DCE Connectivity Hardware organization, focusing on advanced CMOS digital design, high-speed SerDes, silicon validation, and multi-generational product execution.
Locations (8)
Santa Clara, California, United States
Irvine, California, United States
Ottawa, Ontario, Canada
Pavia, Pavia, Italy
Aachen, North Rhine-Westphalia, Germany
Bucharest, Bucharest, Romania
Show all 8 locations
Vietnam
India
Compensation
$242,080 - $362,600 per annum
Responsibilities
Lead a globally distributed engineering organization spanning design, verification, physical design, DFT, and/or silicon validation
Own end-to-end execution of one or more major product families — from RTL design through tape-out, bringup, and production release
Drive first-silicon success across next-generation 200G/lane and beyond connectivity products on 3nm and 2nm process nodes
Establish and continuously improve design flows, verification methodologies, DFT strategies, and emulation infrastructure to accelerate delivery and quality
Partner with architecture, systems, and product management teams to define the technical roadmap for next-generation connectivity products
Own the bringup and New Product Introduction (NPI) phases to enable custom silicon products, validating ASIC subsystems such as boot, PCIe, memory (e.g., HBM, SRAM), compute cores, and power.
Own the bringup and New Product Introduction (NPI) phases to enable custom silicon products, validating ASIC subsystems such as boot, PCIe, memory (e.g., HBM, SRAM), compute cores, and power.
Design, develop, operate, and maintain detailed validation tests and test plans in coordination with cross-functional architecture, design, and software teams.
Perform system characterization, qualification, and debugging to root-cause failures across both pre-silicon prototyping platforms and post-silicon production.
Provide feedback to improve critical features like power management quality, performance, and reliability through successive generations of designs.
Partner with customers, systems, manufacturing, diagnostics, and vendor teams to resolve issues and eliminate failures by "shifting left" in the production and deployment lifecycle.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
Nice to have: Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
As a Senior Manager in Silicon Design Validation, You lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products, providing strategic oversight and technical direction across the full post-silicon lifecycle.
Responsibilities
Lead a highly motivated team focused on ensuring the quality and performance of advanced semiconductor products
Foster a learning environment where engineers gain hands-on experience with FPGA architectures and foundational IP blocks
Oversee the validation and characterization of analog, digital, and mixed-signal IPs
Guide the development of validation plans, including bench hardware and software requirements
Supervise the creation of custom RTL test logic to support targeted validation and characterization efforts
Own end-to-end talent acquisition for Lattice Semiconductor's engineering organization, focusing on niche semiconductor talent in India and expanding to US and global markets.
Responsibilities
Own end-to-end recruiting from sourcing through offer close for niche FPGA/semiconductor talent
Build and execute proactive deep sourcing strategies for niche technical talent
Source passive candidates through unconventional channels
Partner closely with local India hiring managers to build full end-to-end recruiting ownership
Track hiring metrics and provide data-driven insights on market dynamics
Requirements
Master's degree in HR, Business, or Engineering-related field
Nice to have: hardcore sourcing experience across North America, APAC, and India
Nice to have: startup or high-growth product company experience
Nice to have: building talent pipelines in competitive semiconductor markets
We are seeking a Principal FPGA Micro-Architect with deep expertise in programmable logic fabric design and a track record of delivering next-generation FPGA devices from concept to silicon.
Compensation
Base Pay Range 250,000.00. In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Drive fabric PPAU (power, performance, area, and utilization) optimization; evaluate implementation and routing feasibility and drive design trade-offs for modularity and scalability across device generations
Develop SystemC/C++ architectural models to drive performance analysis and evaluate fabric design trade-offs ahead of RTL/schematic availability
Lead advanced low-power fabric design including clock and power islands, power gating, dual-rail architectures, and dynamic power mode switching
Drive software primitive definition and implementation strategy, ensuring fabric elements are optimally mapped to CAD tools and customer design flows for maximum usability
Seeking an expert and innovative Director of NAND Design for Test (DFT) to lead the global DFT strategy, architecture, and execution for advanced NAND Flash products at Micron Semiconductor Italia.
Responsibilities
Define and lead the global NAND DFT vision, strategy, and technical roadmap across product programs and technology generations.
Own DFT architecture, methodology, integration, verification, coverage closure, and design sign-off from early product definition through tape-out.
Partner with Design and Project teams to embed testability early and resolve performance, power, area, reliability, cost, and schedule trade-offs.
Drive reusable methodologies, automation, and DFT and design-for-debug innovation.
Build, develop, and inspire a high-performing global DFT organization.
Lead complex ASIC/SoC development programs from concept through silicon production and product release.
Responsibilities
Lead end-to-end ASIC/SoC development programs
Develop, maintain, and manage integrated program plans, schedules, milestones, dependencies, and critical paths
Coordinate closely with architecture, digital design, analog design, verification, physical design, DFT, CAD, product engineering, packaging, foundry, and operations teams
Drive program reviews, monitor progress, identify risks, and implement mitigation plans
Establish clear ownership, accountability, governance, and escalation processes
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
Nice to have: Master's degree in Engineering, Computer Science, or Business Administration
Nice to have: PMP certification
Nice to have: advanced technology nodes (3nm, 2nm, and beyond)
Senior Hardware Architect focused on Reliability, Availability, and Serviceability (RAS) for Tegra System-on-Chips.
Compensation
Your base salary will be determined based on your location, experience, and other objective job-related factors. The expected base salary ranges for this position are: 184,000 USD – 287,500 USD for Level 4; and 224,000 USD – 356,500 USD for Level 5.
Responsibilities
Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
Work closely with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
Understand the broader SoC architecture and identify how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
Requirements
MS or PhD degree in computer engineering, electrical engineering, or equivalent experience.
Senior Silicon Validation EngineerGoogle · Sunnyvale, US
Design / DFT Director (NVE Engineering)Micron Technology · Avezzano, Italy
Technical Project Manager 3Nokia Global Career Site · India