- Caesarea, Haifa District, Israel
- Senior
- 5+ years
Senior Signal Integrity Engineer responsible for ensuring performance and reliability of high-speed SerDes IP across silicon, package, and board levels.
Responsibilities
- Provide implementation guidelines and feedback to silicon, package, board, and system design teams.
- Design and simulate high-speed SerDes signals and perform co-simulation of package and PCB in HFSS.
- Conduct feasibility studies, design verification, and sign-off processes, including lab correlation.
- Work closely with backend, package, and board design teams for bump-out and ball-out optimization.
- Drive chip-package-PCB co-design of SerDes at 112Gbps and beyond, ensuring signal integrity best practices.
Requirements
- M.Sc. or Ph.D. in Electrical Engineering, Electromagnetics, Physics, or a relevant related field.
- Nice to have: Familiarity with networking technologies and high-speed connectivity solutions
- Nice to have: strong analytical and problem-solving skills
