Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Responsibilities
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Participates in the development and improvement of physical design methodologies and flow automation.
Experienced Core Physical Implementation Engineers to support advanced ASIC and SoC development, focusing on digital physical implementation from RTL-to-GDSII.
Help build the tools, flows and automation our physical design teams use to tape out high-performance ASICs and mixed-signal chips.
Compensation
$154,000—$175,000 USD
Responsibilities
Develop, maintain and extend our physical design flows from synthesis through signoff (place-and-route, CTS, STA, power integrity, DRC/LVS), mostly in Python and TCL.
Use AI and LLM-based tools to automate flow tasks such as report triage, debug, constraint checking, DRC/LVS analysis, run monitoring and QoR prediction.
Research and prototype new flow capabilities, EDA tool features and methodologies, then turn the successful ones into production flows.
Build tools for regression testing, QoR tracking and dashboards so flow changes are measurable and safe.
Support the implementation teams by debugging flow problems, reproducing tool issues and working with EDA vendors on fixes.
Handle all aspects of SOC implementation from netlist to final GDS including floor-planning, partitioning, place & route, timing optimization, scan mode timing, clock tree insertion, and static timing analysis
Responsible for power grid analysis, signal integrity analysis, and physical, electrical, and formal verification
Lead physical design and verification for SOC implementation, including floor‑planning, place & route, timing optimization, power grid analysis, signal integrity, and formal verification.
Responsibilities
Handle all aspects of SOC implementation from netlist to final GDS
Perform floor‑planning, partitioning, place & route (P&R), timing optimization, scan mode timing, clock tree insertion, and static timing analysis (STA)
Conduct power grid analysis, signal integrity analysis, and physical, electrical, and formal verification
Debug LVS/DRC issues at chip/block level
Work independently and collaborate with cross‑functional teams
Join an experienced physical design team working on AMD graphics IP for next-generation AI data center chips. In this role, you will own and drive complex physical design work for multi-million-gate blocks, delivering designs against challenging performance, power, and area targets using advanced process technologies.
Locations (2)
Austin, Texas, United States
Santa Clara, California, United States
Responsibilities
Own the physical design of complex, multi-million-gate graphics IP blocks and drive designs toward required performance, power, and area targets.
Partner with RTL design teams to identify frequency bottlenecks and address logic-level and timing issues early in the project lifecycle.
Drive floorplanning, power planning, synthesis, placement, clock tree synthesis, routing, extraction, timing closure, and physical verification.
Perform and support DRC/LVS verification, crosstalk analysis, and EM/IR analysis through final design signoff.
Establish and improve physical design methodologies for large IP delivery, including IP integration and design-quality checks.
Lead and develop technical solutions in backend digital design implementation and signoff for Cadence customers.
Compensation
The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Hands‑on work with Cadence customers in Backend Digital Design Implementation and Signoff
Lead technical campaigns and strategies in the RTL to GDSII digital implementation space
Aggressively push Power, Performance, and Area (PPA)
Deliver technical presentations and lead discussions internally and with customers
Work closely with R&D to enhance tools and methodologies
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