Referso Jobs

RTL2PD Design Engineer (ASIC)

Inabia Software & Consulting Inc. · Posted Nov 9, 2026

Open

Bay Area, California, United States
Senior
8–12 years

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RTL2PD Design Engineer (ASIC)

Inabia Software & Consulting Inc. · Posted Nov 9, 2026

Open

Bay Area, California, United States
Senior
8–12 years

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Front End Design Engineer

Apple · Posted Nov 5, 2026

Open

Austin, Texas, United States
On-site
Full-time
1+ years

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Convert RTL designs into netlists using industry-standard RTL synthesis tools and optimize power, performance, and area.

Responsibilities

Convert RTL designs into netlists using industry-standard RTL synthesis tools
Optimize power, performance, and area by experimenting with synthesis recipes and enhancing existing synthesis methodologies
Understand RTL code written in Verilog and SystemVerilog languages, correlate it to gate-level circuits, and guide the development of optimal RTL solutions
Perform Clock and Reset Domain Crossing (CDC,RDC) checks to ensure the design's robustness against metastability-related problems and lint checks
Perform logical equivalence checks to ensure correctness of the generated netlist and support ECO generation activities

Requirements

Master's degree in Electrical and Computer Engineering, Electrical Engineering, or a related field

Skills

RTL synthesis Design Compiler Genus Verilog SystemVerilog

Applications Engineering, Sr Staff Engineer

Synopsys · Posted Nov 3, 2026

Open

Bengaluru, Karnataka, India
Senior
10+ years

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Lead application engineering for advanced node ASIC design, deploying Fusion Compiler and ICC2, solving complex PPA challenges and driving customer success.

Responsibilities

Deploy Fusion Compiler and ICC2 on customer designs at advanced nodes
Work directly with customers to develop, debug, and optimize RTL to GDS implementation flows
Run competitive benchmarks to demonstrate Synopsys implementation solutions
Translate customer findings into clear, actionable requirements for Synopsys R&D
Lead customer migration to new EDA tool versions

Requirements

Bachelor's or Master's in Electrical Engineering, Computer Engineering, or equivalent practical experience

Skills

physical implementation placement optimization CTS routing RTL to GDS full flow debugging

RTL Design Engineer

Inabia Software & Consulting Inc. · Posted Nov 4, 2026

Open

Bay Area, California, United States
On-site
Senior
8–12 years
Visa sponsorship

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An RTL Design Engineer role for ASIC design focusing on RTL to Physical Design (RTL2PD) stages, including synthesis, constraint writing, and static timing analysis.

Responsibilities

RTL Synthesis
Constraint writing
validation
Static timing Analysis
Writing/Modifying scripts for RTL synthesis, SDC creation, STA

Requirements

Nice to have: 16nm nodes
Nice to have: 7nm nodes

Skills

RTL Synthesis Constraint writing validation Static timing Analysis RTL to Physical Design (RTL2PD)SDC creation Design compiler PrimeTime Tempus Genus

Applications Engineering, Staff Engineer

Synopsys · Posted Oct 30, 2026

Open

Shanghai, China +1 more
Senior
3+ years

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Lead technical engagements and optimize EDA flows for high-performance compute designs across Asia-Pacific.

Locations (2)

Shanghai, China
Mountain View, California, United States

Responsibilities

Drive technical engagements with customers across Asia-Pacific on high-performance compute designs
Deploy and optimize Fusion Compiler implementation flows to solve PPA challenges
Develop and debug RTL-to-GDSII methodologies in collaboration with customer design teams
Reproduce customer design issues in-house and provide actionable solutions
Translate customer findings into detailed enhancement requests for Synopsys R&D

Requirements

Bachelor's or Master's degree in Electrical Engineering or equivalent technical discipline

Skills

synthesis

Applications Engineering, Staff Engineer

Synopsys · Posted Oct 29, 2026

Open

Shanghai, China +1 more
Senior
3+ years

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Locations (2)

Shanghai, China
Mountain View, California, United States

Responsibilities

Drive technical engagements with customers across Asia-Pacific on high-performance compute designs
Deploy and optimize Fusion Compiler implementation flows to solve PPA challenges
Develop and debug RTL-to-GDSII methodologies in collaboration with customer design teams
Reproduce customer design issues in-house and provide actionable solutions
Translate customer findings into detailed enhancement requests for Synopsys R&D

Requirements

Bachelor's in Electrical Engineering
Master's in Electrical Engineering

Skills

synthesis physical implementation

App Dev Engr/Scient, Inter

Keysight · Posted Jul 14, 2026

Open

Noida, Uttar Pradesh, India
Intern
3+ years

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Validate new PowerArtist features, enhancements, and bug fixes across diverse design environments and customer use cases.

Responsibilities

Validate new PowerArtist features, enhancements, and bug fixes across diverse design environments and customer use cases.
Develop and maintain feature validation test plans, design suites.
Perform functional, performance, and quality verification of RTL power analysis flows.
Reproduce, analyze, and debug customer-reported issues in collaboration with R&D and AE teams.
Create testcases to verify bug fixes and ensure no regressions are introduced.

Skills

RTL design verification power analysis EDA tool validation Verilog SystemVerilog digital design fundamentals AI/ML and Generative AI technologies

RTL2PD Design Engineer (ASIC)

RTL2PD Design Engineer (ASIC)

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Requirements

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Front End Design Engineer

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Applications Engineering, Sr Staff Engineer

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RTL Design Engineer

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Applications Engineering, Staff Engineer

Locations (2)

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Applications Engineering, Staff Engineer

Locations (2)

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App Dev Engr/Scient, Inter

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Design compiler jobs

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Locations (2)

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Locations (2)

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