Design and develop digital portions of battery gauge mixed-signal SOCs, from micro-architecture to RTL and production-ready hardware.
Responsibilities
Collaborate with system and analog design to define digital micro-architecture specifications and implement the RTL that realizes them.
Drive the full digital flow from RTL to physical layout (RTL-to-GDSII), applying and advancing industry best practices, and guide fellow team members through it.
Partner with Design Verification, Validation, Product Engineering, and Test Engineering to ensure a smooth, first-pass transfer to production.
Interface with internal and external stakeholders to understand design requirements, solve problems, and lead technical discussions.
Explore opportunities to optimize and improve digital designs and help evolve architectures over time.
Design and develop advanced components of the memory sub-system and related logic for Microsoft’s cloud hardware infrastructure.
Compensation
Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.
Responsibilities
Be part of a design team developing advanced components of the memory sub-system
Develop automation and AI based solutions to improve organizational efficiency
Own design blocks within complex, coherent fabrics, and bridge IPs
Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc
Collaborate with team members to define interfaces and make optimal design choices
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
As a Wireless SOC Design Verification Engineer, you'll be at the heart of the chip design effort — owning a meaningful verification scope and growing it project to project. You'll work alongside DV methodologists, designers, architects, communication systems engineers, and firmware engineers to build reusable testbenches and verification environments using the latest metric-driven verification methodology.
Responsibilities
Pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff.
Focus at block level, subsystem level, or top-level SOC, including end-to-end simulations of the entire data/control path.
Build reusable testbenches and verification environments using the latest metric-driven verification methodology.
Apprentice (Technical-Engineer) – hands‑on training in transistor‑level simulation, CMOS analysis, and library development within Synopsys’s silicon design ecosystem.
Responsibilities
Run transistor‑level simulations on digital standard cells using PrimeSim or FineSim
Analyze CMOS circuit behavior at the transistor level
Support characterization and validation of standard cell libraries
Document simulation results and circuit‑level observations
Collaborate with library development engineers to improve characterization methodologies
Requirements
Completed B.E/B.Tech in Electronics and Communication Engineering
Work closely with design and architecture teams to develop and execute verification plans for hardware designs using System Verilog, UVM, Python, Perl, and other tools.
Locations (2)
Cupertino, California, United States
United States
Compensation
The base pay range for this role is between $150,400 - $225,300/yr
Responsibilities
Develop verification plans, test benches, tests, and coverage plans
Implement tests in System Verilog, UVM, and C
Automate verification flows using Python, Perl or other scripting languages
Run simulations on CAD software and create regressions
Track bugs and file bug reports until closure
Requirements
Bachelor's degree or foreign equivalent in Electrical Engineering and Computer Sciences, Electrical Engineering, Electronics Engineering or related field
Digital IC Design EngineerNewTexas Instruments · Dallas, US
Junior Wireless SoC Design Verification EngineerNewApple · Israel
Apprentice (Technical-Engineer)Synopsys · Bengaluru, India
Sr. Manager Product Development EngineerAdvanced Micro Devices, Inc · Austin, US