The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead the architecture and design of complex CPU subsystems for next‑generation high‑performance networking switch ASICs
Use expertise in all stages of ASIC development from specification and RTL design through post‑silicon bring‑up
Collaborate closely with SDK, board‑support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms
Requirements
Bachelor's degree
Master's degree
PhD
Nice to have: Leading CPU/SoC subsystem architecture
Lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.
Compensation
The starting salary range posted for this position is $186,900.00 to $267,700.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Lead architecture and design of CPU subsystems
Use expertise in all stages of ASIC development from specification and RTL design through post-silicon bring-up
Collaborate closely with SDK, board-support package (BSP), and Network OS (NOS) software teams to define driver interfaces, register maps, and memory consistency models
Support early emulation and FPGA platforms
Requirements
Bachelor’s + 8 years of related experience
Master’s + 6 years of related experience
PhD + 3 years of related experience
Nice to have: CPU/SoC subsystem architecture
Nice to have: high-performance networking or data-center SoCs
Senior ASIC Design Engineer responsible for building high-speed ASICs from specifications to final netlist, implementing designs in Verilog/System Verilog, and collaborating with physical and verification teams.
Compensation
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 158,500 - 321,000 in California
Responsibilities
Produce detailed micro-architecture specifications from functional specifications
Implement designs using Verilog or System Verilog
Write functional coverage/SVA for verification
Collaborate with Physical Design team for floorplan and timing closure
Work with Verification team to validate blocks
Requirements
Bachelor’s degree in Electrical Engineering
Master’s degree in Electrical Engineering (desired)
Nice to have: Computer Architecture
Nice to have: Networking protocols
Nice to have: Coding skills in Verilog/System Verilog
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 158,500 - 321,000 in California
Responsibilities
Start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements
Implement the design using Verilog or System Verilog
Write functional coverage/SVA to help verification catch corner case bugs
Work with the Physical Design team for optimal floorplan and timing closure
Identify and fix timing in RTL to meet the frequency target
The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level. – United States of America: Annual Salary USD 158,500 - 321,000 in California The listed salary range reflects base salary. Variable incentives may also be offered.
Responsibilities
Start with a functional specification of a module and produce a detailed micro-architecture specification that meets the power/area requirements.
Implement the design using Verilog or System Verilog.
Write functional coverage/SVA to help verification catch corner case bugs.
Work with the Physical Design team for optimal floorplan and timing closure.
Identify and fix timing in RTL to meet the frequency target.
RTL Design Engineer for Mixed-Signal IPs responsible for developing, integrating, and verifying digital RTL blocks within mixed-signal subsystems.
Responsibilities
Develop synthesizable, high-quality RTL for mixed-signal IPs such as ADC/DAC interfaces, PLL/DLL control, power management units, and sensor front-ends.
Collaborate with analog design engineers to define digital-analog interface specifications, control logic, and communication protocols.
Ensure correct functionality and performance of mixed-signal IPs through behavioral modeling, simulation, and co-verification with analog components.
Participate in design reviews, micro-architecture definition, and documentation of IP functionality and timing interfaces.
Perform design quality checks including lint, CDC, RDC, and synthesis readiness analyses.
Requirements
B.E./B.Tech or M.S./M.Tech in Electrical Engineering, Electronics, or Computer Engineering
Oversees definition, design, verification, and documentation for SoC development, driving architecture, design, implementation, and optimization of complex digital logic for next-generation NAND Flash memory–based SSD controllers.
Compensation
The compensation range for this role is $167,360 - $267,800.
Responsibilities
Architect, design, and implement complex RTL modules using Verilog/SystemVerilog
Translate system and microarchitecture specifications into efficient, synthesizable RTL
Design and optimize controller pipelines, state machines, arbitration logic, queues, FIFOs, DMA engines, and memory interfaces
Develop and optimize hardware logic for NAND command sequencing, interface control, data transfer, status handling, error recovery, and timing management
Requirements
Master's or PhD degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field
Good in understanding RTL Design and Digital concepts
Subsystem or SoC integration
Integration 1P and 3P IP's, generating 3P fabrics, quality checks and PD handoff etc.
SS integration using verilog/system verilog, synthesis, timing constraints, floor-planning considerations, performance optimization, and design-quality closure including CDC, Lint, and RDC, register integration
Highly experienced LINT, CDC, and RDC Verification Expert to drive methodology development, qualification, deployment, and signoff across complex SoC and IP programs.
Responsibilities
Define and maintain LINT, CDC, and RDC signoff methodologies for IP, Subsystem, and SoC development.
Drive deployment and qualification of EDA solutions across multiple projects.
Establish best practices, waiver management processes, and signoff criteria.
Lead technical reviews and provide guidance on structural verification issues.
Perform RTL quality checks using Questa Lint and VC SpyGlass Lint.
Lead project activities and mentor less experienced engineers; architect, specify, implement, simulate, and benchmark MCU and DSP systems and hardware accelerators; contribute to design methodology and flow improvements; consult product integration teams; participate in verification and FPGA prototyping; coordinate SDK development with software team.
Responsibilities
Lead project activities and mentor less experienced engineers
Architect, specify, implement, simulate, and benchmark MCU and DSP systems as well as hardware accelerators
Contribute to design methodology and design flow improvements
Consult the product integration teams in the definition, the integration and use of these systems
Participate to the verification and FPGA prototyping of these systems
Requirements
Minimum BS/MS in Electrical Engineering or a related technical field
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