Develop/support automated block and full chip level signoff flows, Full Chip Timing/Noise convergence and full signoff for high quality TO, Enable hierarchical Timing flows, Power optimizations, Generate block level budget and context for correlation with Full Chip, Drive custom IP integration and custom timing checks flows, Close work with Design, DFT, architecture and Power team.
Locations (2)
Haifa, Haifa District, Israel
Herzliya, Tel Aviv District, Israel
Responsibilities
Develop/support automated block and full chip level signoff flows
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enable hierarchical Timing flows
Power optimizations
Generate block level budget and context for correlation with Full Chip
Requirements
Nice to have: Noise and signal integrity effects
Nice to have: Timing margins from synthesis to signoff
Develop and support automated block and full chip level signoff flows, enable hierarchical timing flows, perform power optimizations, generate block level budgets, drive custom IP integration and timing checks, and collaborate with design, DFT, architecture and power teams.
Locations (2)
Haifa, Haifa District, Israel
Herzliya, Tel Aviv, Israel
Responsibilities
Develop/support automated block and full chip level signoff flows
Full Chip Timing/Noise convergence and full signoff for high quality TO
Enable hierarchical Timing flows
Power optimizations
Generate block level budget and context for correlation with Full Chip
Performs physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.
Responsibilities
Conducts all aspects of the physical design flow including synthesis, place and route, clock tree synthesis, floor planning, static timing analysis, power/clock distribution, reliability, and power and noise analysis.
Conducts verification and signoff including formal equivalence verification, static timing analysis, reliability verification, static and dynamic power integrity, layout verification, electrical rule checking, and structural design checking.
Analyzes results and makes recommendations to fix violations for current and future product architecture.
Participates in the development and improvement of physical design methodologies and flow automation.
Help build the tools, flows and automation our physical design teams use to tape out high-performance ASICs and mixed-signal chips.
Compensation
$154,000—$175,000 USD
Responsibilities
Develop, maintain and extend our physical design flows from synthesis through signoff (place-and-route, CTS, STA, power integrity, DRC/LVS), mostly in Python and TCL.
Use AI and LLM-based tools to automate flow tasks such as report triage, debug, constraint checking, DRC/LVS analysis, run monitoring and QoR prediction.
Research and prototype new flow capabilities, EDA tool features and methodologies, then turn the successful ones into production flows.
Build tools for regression testing, QoR tracking and dashboards so flow changes are measurable and safe.
Support the implementation teams by debugging flow problems, reproducing tool issues and working with EDA vendors on fixes.
The candidate will be responsible for designing, developing, verifying, and optimizing integrated circuits (ICs) for advanced semiconductor and SoC applications.
Responsibilities
Develop and implement RTL designs using Verilog and SystemVerilog
Work on ASIC and SoC design and development
Perform RTL coding, simulation, debugging, and functional verification
Support synthesis, timing analysis, and design optimization
Collaborate with physical design, verification, and hardware engineering teams
Requirements
Bachelor's or Master's degree in Electronics and Communication Engineering (ECE), Electrical Engineering, VLSI, or a related discipline
Take part in the large scale SoC physical design cycle from netlist to tape-out, including full flow of back-end implementation and verification always meeting schedule and design goals.
Responsibilities
Own block level PnR, floor-planning, clock and power distribution
Get involved with static timing closure with commercial tools
Do power & noise analysis (EM/IR-Drop/Xtalk) as well as layout verification (DRC/LVS)
Develop and validate dedication low power clock network guidelines
Resolve design and flow issues related to physical design and identify potential solutions
As a Senior FPGA Design & Timing Modeling Engineer, you will work at the intersection of FPGA circuit design, silicon characterization, and software device modeling. You will help translate the behavior and performance of AMD FPGA hardware into accurate timing models used by Vivado to compile, analyze, and optimize customer designs.
Responsibilities
Generate simulation based delays using existing hardware designs to match FPGA timing arcs as per the device model
Develop automation flows to improve FPGA timing quality
Drive silicon based characterization of FPGA resources and root cause any mis-correlation with the expected timing model
Performance analysis on complex designs using Vivado tool
Coordinate release readiness reviews and manage risk mitigation plans
Requirements
Bachelors or Masters degree in Computer Science/Electrical Engineering
Responsible for digital implementation from synthesized netlist through final GDSII release, including floorplanning, power planning, place-and-route, clock-tree synthesis, timing closure, physical verification, power integrity analysis, and tapeout signoff.
Responsibilities
Drive block-level and full-chip physical design implementation from netlist to GDSII
Develop and execute floorplanning, power planning, placement, clock-tree synthesis (CTS), routing, and physical optimization flows
Own timing closure across multiple operating modes including functional, scan shift, and scan capture modes
Develop, optimize, and maintain CTS methodologies and scripts to support complex clock architectures and scan requirements
Perform static timing analysis (STA) and resolve setup, hold, clock skew, insertion delay, transition, and timing constraint violations
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
Lead and own digital ASIC blocks from requirements through RTL implementation, verification, and silicon delivery for next-generation SSD controllers and storage solutions.
Compensation
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
Responsibilities
Own digital ASIC blocks from requirements and microarchitecture definition through RTL implementation, verification support, and silicon delivery.
Develop clear microarchitecture specifications documenting interfaces, data flows, design tradeoffs, and implementation details.
Write synthesizable Verilog or SystemVerilog RTL that meets functional, performance, power, and area requirements.
Run and resolve findings from RTL lint, clock domain crossing (CDC), and synthesis tools to improve design quality.
Collaborate with design verification engineers to develop verification plans, debug simulations using tools such as Synopsys VCS, and resolve functional issues.
Requirements
Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
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