The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up, supporting various phases of SoC DFT-related activities for Broadcom APD’s designs.
Compensation
The annual base salary range for this position is USD 121,900.00 To USD 195,000.00
Responsibilities
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release
Validating & Debugging Test vectors on ATE during the silicon bring up phase
The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up, supporting various phases of SoC DFT-related activities including test insertion, pattern generation, coverage improvement, and basic silicon debug.
Compensation
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00.
Responsibilities
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release
Validating & Debugging Test vectors on ATE during the silicon bring up phase
Incumbent will be responsible for Scan insertion and validation, BIST, MBIST insertion and validation, ATPG, IP tests and Pattern Validation w/wo Timing, DFT mode timing analysis and sign off.
Be responsible for a comprehensive DFT plan and drive the implementation.
Work with DFT and cross functional teams
Hands on experience in various DFT aspects like Scan insertion, MBIST and JTAG, ATPG, Pattern validation at block level as well as Full-chip level
Senior ASIC Engineer responsible for DFT design, verification, and integration.
Responsibilities
Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development for high performance, high quality, low power products
Requirements
Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
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