As a Wireless SOC Design Verification Engineer, you'll be at the heart of the chip design effort — owning a meaningful verification scope and growing it project to project. You'll work alongside DV methodologists, designers, architects, communication systems engineers, and firmware engineers to build reusable testbenches and verification environments using the latest metric-driven verification methodology.
Responsibilities
Pre-silicon RTL verification at the block, subsystem, and top-level SOC, taking your scope from test planning through coverage closure and signoff.
Focus at block level, subsystem level, or top-level SOC, including end-to-end simulations of the entire data/control path.
Build reusable testbenches and verification environments using the latest metric-driven verification methodology.
Research, design, develop, and/or test operating systems for semiconductor operations, applying principles of computer science, engineering, and mathematical analysis.
Responsibilities
Research, design, develop, and/or test operating systems for semiconductor operations
Provide guidance to upcoming developers and provide long range strategy
Develop software systems and tools in support of design, infrastructure and technology platforms
Troubleshoot and debug PC systems
Provide root cause analysis guidance to internal design teams
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
Compensation
$231,500 - $330,000 USD
Responsibilities
Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems
Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives
Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models
Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs
Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline
Lead CPU architecture and performance design for Google’s SoC products, driving microarchitecture features, performance modeling, and integration with system teams.
Plan and evaluate CPU architecture features from both architecture and performance angles.
Develop a performance model for performance analysis and microarchitecture design study.
Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon performance correlation, and post-silicon performance analysis and debugging.
Collaborate with other teams, such as RTL design, design verification, and physical design, to develop a high performance and efficient CPU implementation.
Architect chips or chip-subsystems by analyzing data, writing specifications, coordinating, and negotiating with stakeholders, and creating solutions.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Nice to have: PhD in Electrical Engineering, Computer Engineering, or Computer Science
Nice to have: 12 years of experience with microprocessor architecture
Nice to have: leading CPU and SoC performance model development
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