Static Timing Analysis (STA) jobs

Define low power verification strategies and methodologies for complex ASIC designs.
Author comprehensive low power verification plans targeting UPF‑defined power domains and states.
Develop power‑aware testbenches and simulation environments using SystemVerilog and UVM.
Verify power intent utilizing static low power verification tools like VC LP or Conformal LP.
Run gate‑level simulations with power‑aware models to validate power‑up and power‑down sequences.

Requirements

Nice to have: low‑power digital design
Nice to have: advanced process nodes
Nice to have: Verilog
Nice to have: VHDL
Nice to have: SystemVerilog

Skills

ASIC design ASIC verification physical verification tools DRC

RTL2PD Design Engineer (ASIC)

Inabia Software & Consulting Inc. · Posted Nov 9, 2026

Open

Bay Area, California, United States
Senior
8–12 years

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Seeking an RTL2PD Design Engineer with strong experience in timing constraints, RTL synthesis, and static timing analysis for ASIC multi-node designs.

Responsibilities

RTL Synthesis
Constraint writing
validation
Static timing Analysis
Writing Scripts/Modying scripts for RTL synthesis, SDC creation, STA

Requirements

Nice to have: 16nm experience
Nice to have: 7nm experience

Skills

RTL Synthesis Constraint writing validation Static timing Analysis SDC creation RTL2PD Design compiler PrimeTime Tempus Genus

Design/SDC Engineer

Inabia Software & Consulting Inc. · Posted Nov 9, 2026

Open

San Jose, California, United States
On-site
Contract · Senior
7+ years

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A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.

Responsibilities

Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.

Requirements

Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
Nice to have: TCM (Timing Constraint Manager)
Nice to have: CCD (Conformal Constraint Designer)
Nice to have: Spyglass CDC

Skills

ASIC experience block/full chip SDC development Static Timing Analysis

Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor · Posted Sep 15, 2026

Open

Penang, Malaysia
10+ years

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Design and validate FPGA timing models, ensuring alignment with IP specifications and FPGA tool requirements.

Responsibilities

Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
Perform quality checks on timing models to confirm all timing arcs meet software requirements.
Address issues such as missing timing arcs and missing clock information.
Generate timing reference models based on IP requirements.

Skills

FPGA timing model PrimeTime Liberate Cadence Virtuoso SPICE System Verilog synthesis static timing analysis floor-planning

Sr. Staff Design Engineer

Lattice Semiconductor · Posted Nov 3, 2026

Open

San Jose, California, United States
Senior
$219K–$219K per year
8+ years

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Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.

Compensation

Base Pay Range 218,889.00

Responsibilities

Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
Analyzing hardware capabilities and contributing to customer solution strategies.
Architecting Soft IPs with detailed technical specifications and coordinating development efforts.

Requirements

Bachelor's in Electronics Engineering
Bachelor's in Applied Physics

Skills

RTL design Logic verification Debug Timing closure DDR protocols (DDR3, DDR4, LPDDR4, DDR5)

RTL Engineer – Physical AI Solutions

Altera · Posted Nov 5, 2026

Open

San Jose, California, United States
Full-time
$149K–$238K per year
3+ years

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Design, implement, and verify high-performance RTL for FPGA and programmable hardware solutions supporting Physical AI applications.

Compensation

$149.1K - $238.2K USD

Responsibilities

Design and develop RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
Translate architectural specifications into high-quality, synthesizable Verilog/SystemVerilog RTL.
Create microarchitecture specifications and participate in architecture reviews.
Optimize designs for performance, area, power, and scalability.
Collaborate closely with design verification teams to define verification strategies and close functional coverage.

Requirements

Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
Nice to have: Master's or Ph.D. in Electrical Engineering, Computer Engineering, or related discipline
Nice to have: AI acceleration
Nice to have: machine learning
Nice to have: vision-processing

Skills

Verilog SystemVerilog RTL design

Digital Design Engineer

Fortaegis Technologies · Posted Oct 2, 2026

Open

Amsterdam, North Holland, Netherlands
Senior
5+ years

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Design and implement RTL and IP for FPGA and ASIC-based products, ensuring performance, area, power, and schedule targets are met.

Responsibilities

Design and implement RTL based on system-level requirements
Develop, integrate, and maintain custom and third-party IP
Integrate IP and subsystems at the block and top level
Run synthesis and implementation flows and drive timing closure
Perform RTL quality checks and support verification

Requirements

Nice to have: high-speed networking
Nice to have: cryptographic IP
Nice to have: IP evaluation
Nice to have: vendor engagement

Skills

SystemVerilog Verilog VHDL FPGA ASIC AXI AXI-Stream PCIe Ethernet

Silicon Design Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

Austin, Texas, United States
1+ years

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Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing.

Responsibilities

Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Perform definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Contribute to the development of multidimensional designs involving the layout of complex integrated circuits

Requirements

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, Electrical and Computer Engineering, or related field

Skills

hardware and software verification embedded driver development and programming C C++Python Verilog

MTS Silicon Design Engineer

Advanced Micro Devices, Inc · Posted Nov 6, 2026

Open

San Jose, California, United States
Full-time · Senior
3+ years

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Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing, employing knowledge of electronic theory.

Responsibilities

Oversee definition, design, verification, and/or documentation for custom mixed-signal design development.
Determine architecture design, logic design, and/or system simulation.
Define module interfaces/formats for simulation.
Lead the development of multidimensional designs involving the layout of complex integrated circuits.
Participate in product bring-up and debug and contribute to test-plans and characterization reports.

Requirements

Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field

Skills

Mixed-signal circuit design emphasizing Clock Distribution Networks and SI/PI performance for system design Mixed signal design circuit blocks Low power design techniques for high-speed, custom digital circuits Functional verification of microprocessors

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