A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
As an RTL Engineer, you will be responsible for designing, implementing, and verifying high-performance digital logic that powers AI and accelerated computing solutions.
Compensation
$149.1K - $238.2K USD
Responsibilities
Design and develop RTL for FPGA and programmable hardware solutions supporting Physical AI applications.
Translate architectural specifications into high-quality, synthesizable Verilog/SystemVerilog RTL.
Create microarchitecture specifications and participate in architecture reviews.
Optimize designs for performance, area, power, and scalability.
Collaborate closely with design verification teams to define verification strategies and close functional coverage.
Requirements
Bachelor's Degree in Electrical Engineering
Computer Engineering
Computer Science
related technical field
Nice to have: Master's or Ph.D. in Electrical Engineering
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing.
Responsibilities
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Perform definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Contribute to the development of multidimensional designs involving the layout of complex integrated circuits
Requirements
Master’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, Electrical and Computer Engineering, or related field
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing, employing knowledge of electronic theory.
Design and deploy ML, DL, and GenAI tools that translate silicon data into actionable optimized strategies for predictive yield and performance optimization.
Compensation
The annual base salary range for this position is USD 109,700.00 To USD 175,500.00
Responsibilities
Design, build, and deploy ML, DL, and GenAI models to predict and maximize wafer-level yield using large-scale SoC telemetry data.
Organize, clean, and analyze large, multi-source sensor databases and provide input on future telemetry requirements.
Interpret complex parametric data, on-chip sensor readouts, and circuit telemetry to isolate failure mechanisms and marginalities.
Partner with foundry, product engineering, design-for-manufacturing (DFM), DFT engineering teams to drive yield and PPA strategies.
Develop, qualify and productize experimental data workflows, and work with teams to release to scalable production.
Requirements
MS in Electrical Engineering
MS in Computer Science
PhD in Electrical Engineering or Computer Science related field
Perform static timing analysis and related engineering tasks using Cadence tools.
Compensation
The annual salary range for California is $106,400 to $197,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Perform static timing analysis, glitch and noise analysis using Tempus Signoff tool
Execute and deliver timing analysis flows, ECO flows, CAD tools and methodologies
Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, distributed and concurrent STA flows
Collaborate with R&D and customers to enable timing analysis and ECO flows
Perform timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs
Lead and develop technical solutions in backend digital design implementation and signoff for Cadence customers.
Compensation
The annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits.
Responsibilities
Hands‑on work with Cadence customers in Backend Digital Design Implementation and Signoff
Lead technical campaigns and strategies in the RTL to GDSII digital implementation space
Aggressively push Power, Performance, and Area (PPA)
Deliver technical presentations and lead discussions internally and with customers
Work closely with R&D to enhance tools and methodologies
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