Responsible for digital implementation from synthesized netlist through final GDSII release, including floorplanning, power planning, place-and-route, clock-tree synthesis, timing closure, physical verification, power integrity analysis, and tapeout signoff.
Responsibilities
Drive block-level and full-chip physical design implementation from netlist to GDSII
Develop and execute floorplanning, power planning, placement, clock-tree synthesis (CTS), routing, and physical optimization flows
Own timing closure across multiple operating modes including functional, scan shift, and scan capture modes
Develop, optimize, and maintain CTS methodologies and scripts to support complex clock architectures and scan requirements
Perform static timing analysis (STA) and resolve setup, hold, clock skew, insertion delay, transition, and timing constraint violations
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
Lead and own digital ASIC blocks from requirements through RTL implementation, verification, and silicon delivery for next-generation SSD controllers and storage solutions.
Compensation
The salary offered to a selected candidate will be tailored based on several factors, including the location, job grade, relevant knowledge, skills, and experience. We also take into account the internal equity among our current team members to ensure fairness and competitiveness.
Responsibilities
Own digital ASIC blocks from requirements and microarchitecture definition through RTL implementation, verification support, and silicon delivery.
Develop clear microarchitecture specifications documenting interfaces, data flows, design tradeoffs, and implementation details.
Write synthesizable Verilog or SystemVerilog RTL that meets functional, performance, power, and area requirements.
Run and resolve findings from RTL lint, clock domain crossing (CDC), and synthesis tools to improve design quality.
Collaborate with design verification engineers to develop verification plans, debug simulations using tools such as Synopsys VCS, and resolve functional issues.
Requirements
Master’s degree in Electrical Engineering, Computer Engineering, or a closely related field.
Develop automated methodology for chip and silicon IP design, support EDA infrastructure, and contribute to CAD tools and AI-assisted solutions.
Compensation
The US hourly range for this full-time position is $25.80 to $47.80.
Responsibilities
Develop, maintain, and enhance CAD methodologies and automation flows supporting digital ASIC design, verification and implementation.
Work with industry-standard EDA tools across formal verification, synthesis, static timing analysis, power analysis to improve design quality, productivity, and flow efficiency.
Develop Python, Tcl, and shell-based scripts and utilities to automate design workflows, analyze results, and streamline engineering processes.
Explore and develop AI-assisted solutions to address practical challenges in CAD and semiconductor design workflows.
Investigate and deploy applications of large language models (LLMs), retrieval-augmented generation (RAG), and AI agents for engineering automation and intelligent workflow assistance.
A Design/SDC Engineer focused on timing constraints, SDC/STA tools, and seamless physical design closure for next-generation networking chips.
Responsibilities
Being a member of design team who oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing modes.
Option to also do block level RTL design or block or top-level IP integration.
Helping develop efficient methodology to promote block level SDCs to fullchip, and to bring fullchip SDC changes back to block level.
Helping develop and apply methodology to ensure correctness and quality of SDCs as early as possible in design cycle.
Reviewing block level SDCs and clocking diagrams and mentor other RTL design owners on SDC development.
Requirements
Bachelor’s Degree in Electrical or Computer Engineering
Master’s Degree in Electrical or Computer Engineering
Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.
Compensation
Base Pay Range
218,889.00
Responsibilities
Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
Analyzing hardware capabilities and contributing to customer solution strategies.
Architecting Soft IPs with detailed technical specifications and coordinating development efforts.
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