Develop, verify, and field the Next Generation Overhead Persistent Infrared (NG OPIR) space and ground enterprise to deliver resilient Missile Warning (MW) to warfighters for the Space Force’s top-priority space programs.
Compensation
The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD).
Responsibilities
Develop, verify, and field the Next Generation Overhead Persistent Infrared (NG OPIR) space and ground enterprise to deliver resilient Missile Warning (MW)
Develop and execute requirements verification plans
Lead formal requirements sell-off across space and ground segments
Lead verification activities at the enterprise, system, segment, element, and interface levels
Evaluate prime contractor verification evidence
Requirements
Bachelor’s degree in a STEM field, such as an Engineering, Physics, Mathematics, or Computer Science field
Senior Systems Engineer responsible for developing, verifying, and fielding space and ground systems for the Space Force, leading requirements verification and formal sell-offs.
Compensation
The projected compensation range for this position is $86,800.00 to $198,000.00 (annualized USD).
Responsibilities
Develop, verify, and field NG OPIR space and ground enterprise systems
Develop and execute requirements verification plans
Lead formal requirements sell-offs across space and ground segments
Lead verification activities at enterprise, system, segment, element, and interface levels
Maintain traceability in Digital Engineering models
Requirements
Bachelor’s degree in a STEM field such as Engineering, Physics, Mathematics, or Computer Science
Support the development of advanced hypersonic systems and mission-critical defense technologies by developing, maintaining, and integrating system models that support requirements development, system architecture, functional analysis, interface definition, and verification planning throughout the system development lifecycle.
Responsibilities
Develop, maintain, and manage system models using Cameo Systems Modeler or equivalent MBSE tools.
Create and maintain SysML diagrams, including block definition diagrams, internal block diagrams, activity diagrams, state machines, sequence diagrams, and requirements diagrams.
Support the development and refinement of system architectures, functional decompositions, logical architectures, and physical architectures.
Establish and maintain traceability between stakeholder needs, system requirements, functions, interfaces, system components, and verification activities.
Collaborate with systems engineers and subject matter experts to capture technical information and incorporate it into authoritative system models.
In this leadership role within the Engineering Core Team, the candidate will leverage their strong technical understanding of the end-to-end silicon engineering process, from SoC architecture and design through tape-out, post-silicon bring-up and production, to manage and drive the execution activities of cross-disciplinary engineering functions developing semi-custom ASIC solutions in collaboration with one of AMD’s largest customers.
Responsibilities
Plan and drive end-to-end cross-functional technical execution of complex SoC/ASIC programs from architecture and requirements definition through design, verification, implementation, tape-out, post-silicon bring-up, qualification, and production.
Drive AMD product solution deliverables and alignment with customer platforms to ensure the highest level of customer satisfaction throughout the product lifecycle.
Engage with technical leadership to understand and document program scope, establish integrated schedules, identify critical technical dependencies, assess and manage program progress and risk, and create resource and budget plans.
Work closely with SoC Architecture, Design, IP, DV, DFx/DFT, PD, Packaging, Firmware/Software, Validation, Product Engineering, and Manufacturing teams to drive technical readiness and closure of cross-functional issues.
Develop a strong understanding of key program-level technical challenges and drive alignment on architecture, performance, power, area, timing, verification, testability, physical implementation, package, and silicon readiness trade-offs.
As a Senior Requirements Engineer, you will collaborate closely with system integrators, architects, and MBSE teams to define, refine, and document mission planning and component-level specifications, ensuring requirements are clear, consistent, and verifiable.
Compensation
Target Salary Range
$135,000 - $216,000. This represents the typical salary range for this position. Salary is determined by various factors, including but not limited to, the scope and responsibilities of the position, the individual’s experience, education, knowledge, skills, and competencies, as well as geographic location and business and contract considerations. Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay.
Responsibilities
Provide feedback, clarification, and refinement of the Mission Planning Specification in coordination with the System Integrator and architecture teams.
Derive component-level specifications from mission-level requirements and from behaviors represented in the MBSE model.
Ensure requirements are properly captured, traceable, and aligned with system architecture, interfaces, and model behavior.
Support creation of requirement verification artifacts for all mission planning and component-level requirements, ensuring verifiable acceptance criteria.
Collaborate with MBSE practitioners to validate that system behavior, interfaces, and architectures accurately reflect requirement intent.
As a Senior ASIC Design Verification Engineer, you will play a critical role in ensuring the functional correctness and performance of our AI inference ASICs. You will be responsible for developing and executing advanced verification methodologies, working closely with design, architecture, and software teams to validate our silicon solutions.
Compensation
The base salary range for this role is $200,000 – $350,000.
Responsibilities
Develop and execute verification strategies for AI inference ASICs
Define and implement comprehensive test plans and verification methodologies
Lead the development of verification environments using SystemVerilog UVM
Create and maintain simulation testbenches, directed and constrained-random tests
Collaborate with design and architecture teams to ensure functional coverage and closure
Requirements
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
Advanced degree in Electrical or Computer Engineering or related field
Nice to have: hardware-software co-verification
Nice to have: formal verification techniques
Nice to have: post-silicon validation and bring-up methodologies
Serve as a senior cross-functional technical lead supporting the Test Integration & Development Environment for Spacecraft organization, spanning TIDES pillars: System Test Environment hardware, Platform Integration & Evolution firmware, and Standard Software Infrastructure.
Compensation
Combined Salary Range
USD $149,902.00 - USD $166,298.00 /Yr.
Responsibilities
Lead technical coordination across STE, PIE, and SSI scope
Support architecture, design, integration, and verification of development, unit verification, production, module, power converter, NAS and calibration test environments
Translate payload and program requirements into test capabilities, measurement approaches, interface needs, verification methods, and evidence-generation plans
Support design package development, including top-level assemblies, interface control documents, cable packages, rack architecture, RF drawer concepts, FPGA/IO drawer concepts, calibration planning, BOM coordination, and test readiness artifacts
Coordinate FPGA and digital I/O needs across test racks, payload interfaces, data capture paths, timing/reference distribution, and platform evolution plans
Requirements
Bachelor's degree in Systems Engineering, Electrical Engineering, Computer Engineering, Software Engineering, or a related Science, Engineering, or Mathematics field
Lead system-level verification for integrated hardware, firmware, and cloud/application solutions, ensuring compliance with requirements and driving test automation.
Responsibilities
Develop verification plans and procedures mapping requirements to methods
Build and maintain system test case library with end-to-end coverage
Use AI to draft and review test cases and automation scripts
Execute verification, capture evidence, and maintain traceability
Analyze defects across HW/FW/SW boundaries and feed feedback
Requirements
Bachelor’s degree in Electrical/Computer Engineering, Systems Engineering, Computer Science, or related field
The Senior Project Engineer (PE) – Communications & Power Sustainment is the project engineering lead for sustainment of existing communications systems and power products at Leonardo DRS Canada.
Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, Computer Science, or a related technical discipline.
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