Must have SCCM/Intune and Management experience.
6 years in IT engineering and 5+ years in enterprise desktop or end‑user computing roles, including leadership responsibilities. Deep, hands‑on knowledge of Windows in large enterprise environments, including OS deployment, imaging, troubleshooting, and lifecycle management. Endpoint Management Mastery: Expert‑level experience with Microsoft SCCM/MECM and Microsoft Intune, including software distribution, patching, compliance, and co‑management models. VDI & Remote Computing: Strong understanding of virtual desktop technologies (e.g., Citrix, VMware Horizon, Azure Virtual Desktop) and their integration with endpoint environments. Automation & Scripting
This role is not eligible for Sponsorship Now or in Near future.
HYBRID - 3 days onsite must
Lead RTL design methodology and static signoff flows for Ericsson’s 5G and 6G ASIC and FPGA programs.
Locations (4)
Austin, Texas, United States
Stockholm, Stockholm County, Sweden
Lund, Sweden
India, Madhya Pradesh, India
Compensation
The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job-related knowledge, qualifications, skills, education, training, and experience.
Responsibilities
Own RTL design methodology: Define coding guidelines, lint rule sets, waiver policy, and signoff criteria for IP, subsystem, and SoC teams.
Develop, implement, and maintain test methods, procedures, and specifications to verify product functionality and performance for new products.
Compensation
CA San Francisco Bay Area Salary Range for this position: $73,000.00 - $159,000.00.
Responsibilities
Develop, implement, and maintain test methods, procedures, and specifications to verify product functionality and performance for new products.
Participate in design reviews and cross-functional teams to assess test impact, provide Design for Test and Manufacturability feedback, and help define test requirements and acceptance criteria early.
Develop, debug, and improve automated test content using scripting and software tools, using simulators, virtual environments, or bench hardware before the first physical build.
Support during Virtual Build to assess test architecture, fixture needs, facilities, and design stability, and carry findings into physical builds.
Design, validate, and support deployment of test fixtures and test hardware.
Lead and design mission operations systems for Northrop Grumman Space Systems, developing concepts of operations, procedures, tools, and supporting operational rehearsals and demonstrations.
Own, troubleshoot, and solve customers’ technical issues while collaborating across teams and improving product processes.
Compensation
The typical base pay range for this role across the U.S. is USD $70,500 - $139,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $95,000 - $153,200 per year.
Responsibilities
Own, investigate and solve customer technical issues
Collaborate within and across teams using troubleshooting tools
Lead or participate in building communities with peer delivery roles
Develop technical and professional proficiency to resolve customer issues
Identify potential product defects and contribute to product improvements
Requirements
Bachelor's Degree in Computer Science, Information Technology, or related field
Lead and manage fleet fundamentals and quality for Azure hardware infrastructure, driving governance, KPIs, and cross-functional program delivery.
Compensation
Hardware Engineering IC5 - The typical base pay range for this role across the U.S. is USD $142,800 - $274,800 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $188,000 - $304,200 per year.
Responsibilities
Lead and be accountable for the Fleet Fundamentals (Fleet Health & Quality) management of the Azure HW Infrastructure.
Drive fleet management governance best practices including phase gate checklists, waterfall charts, fleet KPIs and forecasting
Be the champion of Fleet Quality and drive quick-turn solutions to improve customer experience on Azure fleet
Defining project scope, goals, and deliverables, and managing the project timeline, budget, and resources.
Developing and maintaining project plans, schedules, and status reports, and communicating project status to stakeholders and senior management.
Requirements
Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field
Nice to have: experience with Azure infrastructure
Nice to have: experience designing or prototyping technical solutions
Senior Technical Program Manager responsible for hardware remediations, quality initiatives, and cross-functional leadership within Microsoft’s Cloud Infrastructure and Hardware Engineering teams.
Compensation
Hardware Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119,800 - $234,700 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $160,200 - $261,000 per year.
Responsibilities
Own and execute critical hardware remediations across the manufacturing spectrum
Influence partners and make key decisions on hardware quality escapes
Identify opportunities to automate workflows and reduce manual work
Perform cost/time/risk tradeoff analysis
Partner with leadership to create inclusive engineering environments
Requirements
Master's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field
Bachelor's Degree in Electrical Engineering, Computer Engineering, Mechanical Engineering, or related field
Lead lint, CDC, and RDC signoff: Architect structural, formal, and hybrid CDC and RDC flows with progressive goals and hierarchical signoff using abstract models and clock/reset constraints.
Build vendor-agnostic flows: Deliver single-command static signoff in OneRun with standard project templates and Jenkins CI quality gates.
Drive RTL reuse and automation: Architect configurable RTL frameworks and standard interfaces for multi-program IP reuse.
Apply AI to RTL engineering: Use and improve AI tools such as ChipAgents and Kiro for RTL development, documentation, code conversion, and lint and CDC triage.
Requirements
Bachelor’s or master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field—or equivalent practical experience.
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