Referso Jobs

Design and verify digital systems for safety‑critical programs
Integrate requirements, processes, procedures and tools into development lifecycle
Collaborate with development leads, scientists, engineering and manufacturing teams
Drive innovation in model‑based engineering, DevSecOps and Agile practices

Requirements

Bachelor's degree in a STEM field
Master's degree in a STEM field
PhD in a STEM field
Nice to have: V&V technologies
Nice to have: System Verilog

Skills

High-Speed Digital Design and Verification FPGA/SOC/ASIC implementation VHDL Verilog Synthesis Timing Closure

Logic Design Engineer

Microsoft · Posted Nov 9, 2026

Open

United States
$102K–$202K per year
5+ years

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Design and develop advanced components of the memory sub-system and related logic for Microsoft’s cloud hardware infrastructure.

Compensation

Silicon Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102,100 - $202,200 per year. There is a different range applicable to specific work locations, within the San Francisco Bay area and New York City metropolitan area, and the base pay range for this role in those locations is USD $133,800 - $219,200 per year.

Responsibilities

Be part of a design team developing advanced components of the memory sub-system
Develop automation and AI based solutions to improve organizational efficiency
Own design blocks within complex, coherent fabrics, and bridge IPs
Be responsible for all aspects of the design flow including RTL coding, Lint, CDC, timing closure, etc
Collaborate with team members to define interfaces and make optimal design choices

Requirements

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field
Doctorate degree in Electrical Engineering, Computer Science, Computer Engineering, or related field
Nice to have: front-end tools
Nice to have: Computer Architecture

Skills

digital logic design

Principal Engineer Digital/Sr Principal Engineer Digital

Northrop Grumman · Posted Nov 9, 2026

Open

Woodland Hills, California, United States
On-site
Full-time · Senior
$125K–$235K per year
5–8 years

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Lead design and verification of digital systems for safety‑critical defense products, driving innovation in digital engineering and supporting the warfighter.

Compensation

Primary Level Salary Range: $125,300.00 - $187,900.00 Secondary Level Salary Range: $156,400.00 - $234,600.00

Responsibilities

Design and verify digital systems on a safety‑critical development program
Integrate requirements, processes, procedures and tools into the development lifecycle
Collaborate with development program leads, senior scientists, engineering and manufacturing organizations
Lead the use of Model‑based Engineering, DevSecOps and Agile practices for enterprise‑wide digital transformation

Requirements

Bachelor's degree in a STEM field
Master's degree in a STEM field
PhD in a STEM field
Nice to have: V&V technologies
Nice to have: System Verilog

Skills

High‑Speed Digital Design and Verification FPGA/SOC/ASIC implementation VHDL/Verilog Synthesis

Lead Digital Design Engineer

Analog Devices, Inc. · Posted Nov 9, 2026

Open

Limerick, County Limerick, Ireland
On-site
Full-time · Lead
4+ years

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As a Lead (Staff) Designer, Digital, you hold a senior technical position working on our most complex digital challenges, developing innovative solutions and serving as a key technical resource and leader for the organization.

Responsibilities

Architect and design digital blocks and complex subsystems.
Write detailed block and subsystem-level specifications for design and implementation.
Use Verilog and SystemVerilog to design digital blocks, subsystems, and top level designs.
Develop block level testbenches, verify block functionality, and collaborate with verification teams to achieve full chip verification and coverage closure.
Perform block and top level linting, CDC analysis, and power analysis. Assist with synthesis, constraints, pnr and timing closure.

Requirements

MSEE
PhD in Electrical Engineering
Nice to have: high-speed SerDes transceiver architectures
Nice to have: silicon bring-up
Nice to have: behavioral modeling

Skills

Verilog SystemVerilog digital IC architecture design CDC analysis

ASICS Design Engineer, Senior

Qualcomm · Posted Nov 9, 2026

Open

Hsinchu City, Taiwan
On-site
Senior
2–10 years

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Lead ASIC design and delivery for Ethernet switch subsystems, driving architecture-aligned implementation, optimization, and integration.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic
Participate in SoC integration with focus on Ethernet switch subsystems
Lead design and delivery of key subsystems in Ethernet switch ASICs
Own micro-architecture and RTL design of networking blocks
Drive subsystem integration, performance tuning, and power optimization

Requirements

Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field

Skills

ASIC design RTL coding verification synthesis timing closure physical design flow ASIC FE design flow

ASICS Design Engineer, Staff

Qualcomm · Posted Nov 9, 2026

Open

Hsinchu City, Taiwan
On-site
Full-time · Staff
2–10 years

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Implement RTL design, synthesis, and timing closure for networking datapath/control logic for Ethernet switch ASICs.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic.
Participate in SoC integration with focus on Ethernet switch subsystems.
Lead design and delivery of key subsystems in Ethernet switch ASICs, driving architecture-aligned implementation and optimization.
Own micro-architecture and RTL design of networking blocks (e.g., forwarding engine, parser, traffic manager).
Drive subsystem integration, performance tuning, and power optimization.

Requirements

MS/BS in EE (MS preferred)
Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field
Nice to have: merchant silicon

Skills

ASIC design logic design RTL coding verification synthesis

Sr. Staff RTL Eng

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
Senior
14+ years

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Senior Staff design engineer responsible for RTL development of machine learning engines on low‑power FPGA platforms.

Responsibilities

Develop and enhance RTL for machine learning engine
Implement ML operators efficiently on low‑power FPGA
Optimize data path for high throughput and low latency
Collaborate with algorithm and architecture teams to translate ML models into efficient hardware micro‑architectures
Design RTL for machine learning compute engines targeting low‑power FPGA platforms

Requirements

BE/MTech/PhD in Electronics, Electrical or Computer Engineering
Nice to have: Experience with C
Nice to have: Experience with SystemC

Skills

RTL design using Verilog RTL design using System Verilog-HDL Functional simulation using Xcelium Functional simulation using Cadence Functional simulation using VCS Functional simulation using Synopsys

Senior Design Engineer(FPGA RTL)

Lattice Semiconductor · Posted Sep 10, 2026

Open

Hyderabad, Telangana, India
Senior
5+ years

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Senior IP Design engineer with extensive FPGA RTL design experience

Responsibilities

Design FPGA RTL logic
Verify logic and perform timing closure
Debug hardware and validate designs
Package soft IP and develop testbenches

Requirements

BS/MS/PhD in Electronics or Computer Engineering
Nice to have: Hardware validation and debug
Nice to have: Soft IP packaging
Nice to have: Example design
Nice to have: Testbench development

Skills

FPGA RTL design Logic verification Debugging Timing closure C/C++Perl TCL Python High-speed IO protocols

Staff Applications Engineer

Lattice Semiconductor · Posted Jul 14, 2026

Open

Penang, Malaysia
Staff
10+ years

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Factory Applications Engineer supporting silicon design and customer enablement for low‑power programmable logic devices.

Responsibilities

Drive silicon feature enablement & improvement for a particular domain
Develop silicon enablement collaterals with focus on usability and performance
Develop and conduct trainings/workshops for sales & tech support team
Provide factory support and guidance to resolve customer issues
Collaborate closely with sales team to understand customer needs & solidify requirements to R&D

Requirements

BS/MS in Electrical Engineering

Skills

FPGA architecture PLL Embedded Memory blocks DSP blocks Input/Output blocks SSTL HSTL LVSTL

Timing closure jobs

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