Drive the development and successful delivery of complex silicon systems.
Compensation
The US base salary range for this full-time position is $236,600 - $278,000 + 20% bonus target + equity + benefits determined by role, level, and location.
Responsibilities
Drive the development and successful delivery of complex silicon systems.
Develop policies, testing procedures, and documentation to maximize efficiency and promote sustainability across deliverables.
Execute comprehensive testing protocols and influence system designs to enhance overall validation and debugging capabilities.
Standardize engineering approaches across programs to reduce technical debt and drive cross-functional innovation.
Guide system architectures by breaking down complex problems, evaluating trade-offs, and reviewing cross-functional designs.
Requirements
Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or a related field
Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
Lead planning and design for campus facilities, overseeing architectural and interior design services, space utilization, and compliance with local ordinances.
Compensation
$100,000.00 $150,000.00 annually. Salary commensurate with education, experience and qualifications. Salary range $102,600.00 - $138,500.00
Responsibilities
Plan and coordinate all tasks, critical dates, campus client relations, performance quality and customer satisfaction, budget and project management, and administration for each assigned project
Provide oversight for a wide range of planning activities that guide the physical development of the campus and the utilization of campus space
Meet with campus clients and work in close collaboration and integration with other administrative departments involved in campus planning and space planning
Lead the discretionary project approvals process, in the pre-design phase of projects, and in project initiation
Prepare and maintain architectural standards and specifications to assure conformance to applicable building codes and safety requirements
Requirements
Bachelor’s Degree in architecture, physical planning, or other closely related field
Lead the development of next-generation connectivity ASICs for cloud and AI infrastructure, focusing on Physical Design CAD methodology and automation.
Compensation
The base salary range for this role is $160,000–$200,000 USD.
Responsibilities
Develop and maintain Physical Design CAD flows and methodologies for advanced process nodes.
Build automation frameworks using Python and Tcl to support synthesis through signoff.
Perform hands‑on Physical Design and PNR, including floorplanning, placement, CTS, routing, and timing closure.
Develop and optimize EDA tool flows for timing analysis, extraction, EM/IR, and physical verification.
Support block‑level implementation from synthesis through GDSII signoff.
Requirements
Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's degree preferred.
Nice to have: 3nm or more advanced process technologies
Nice to have: Automated CAD flows from synthesis through signoff
PLL Design EngineerNewAdvanced Micro Devices, Inc · San Diego, US
Silicon GeneralistNewGoogle · Sunnyvale, US
ASIC Development Technical LeaderCisco · Vancouver, Canada
ASICS Design Engineer, StaffQualcomm · Hsinchu City, Taiwan
Advanced Packaging Development EngineerApple · US
Physical Design and CAD EngineerAstera Labs · San Jose, US