Design and implement power management, reset, and clocking solutions for RISC-V CPU and SoC IP.
Compensation
Base Pay Range
$205,740.00-$251,460.00
In addition to base pay, this role may be eligible for variable/ incentive compensation and/ or equity.
Responsibilities
Work with the architecture team to understand and define power management requirements.
Architect, design and implement core clocking, reset and power management solutions.
Microarchitecture development and specification. Ensure that knowledge is shared via clear documentation and participation in a culture of collaborative design.
Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
Work with a physical implementation team to implement and optimise physical design to meet frequency, area, power goals.
Requirements
BS/MS degree in EE, CE, CS or a related technical discipline, or equivalent experience.
Nice to have: AMBA Interconnect Protocols such as AXI, AHB, and APB
Nice to have: AMBA Low Power Protocol Interface including P-channel and Q-channel protocols
Nice to have: Scala/Chisel, Bluespec, or other language/DSL for expressing configurable hardware via software
Define the Micro-architecture of the CPU hardware. Develop the CPU hardware using a Hardware-Description-Language. Perform functional debug and closure of the design. Responsible for timing and power closure of the design for the target Frequency and Power. Prepare documentation of the Design Specification. Design and develop hardware for Apple's mobile devices. Evaluate new ideas and features for the Central Processing Unit (CPU) hardware.
Compensation
At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $180,294 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation.
Responsibilities
Define the Micro-architecture of the CPU hardware
Develop the CPU hardware using a Hardware-Description-Language
Perform functional debug and closure of the design
Responsible for timing and power closure of the design for the target Frequency and Power
Prepare documentation of the Design Specification
Requirements
Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field
The applicable full salary ranges for this position, by specific state, are listed below: New York City Metro Area: $125,700.00 - $203,100.00 Non-Metro New York state & Washington state: $111,700.00 - $180,800.00
Responsibilities
Implement and optimize low-power design methodologies
Perform block- and full-chip-level power analysis and estimation using Synopsys PrimePower
Physical Design Engineer responsible for taking designs from RTL to GDS, including synthesis, place and route, timing, and physical verification.
Responsibilities
Lead design from RTL to GDS with synthesis, place and route, timing, and physical verification
Automate synthesis and timing-driven place and route of RTL blocks for high-speed datapath and control logic
Automate design flows for clock tree synthesis, clock gating, buffer/repeater insertion, scan stitching, and design optimization
Support floor planning, design methodology, logic equivalence checks, physical/timing/electrical quality checks, and final signoff for large IP delivery
Requirements
Major in EE, CS or related, master’s degree with 3+ years or Bachelor with 5+ years working experience
Nice to have: high-speed multi-gigabit SerDes PHY designs
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