As a data engineer, you’ll work across a dynamic client roster designing and building data solutions that connect media, site, and marketing performance data into actionable insights.
Compensation
Salary Range: $85,000 - 95,000 annually
Responsibilities
Design data solutions that solve client business needs
Partner with analytics and media teams to understand business objectives and translate them into scalable data solutions
Design data models that integrate media, site, sales and media conversion data to provide a complete view of marketing performance
Recommend and implement measurement approaches that support both agency and client objectives
Serve as a subject matter expert on media and marketing data architecture
Requirements
A bachelor’s degree preferred or equivalent work experience in related field such as Computer Science, Data Science, Mathematics/Statistics, Marketing Analytics
Support semiconductor technology development, device characterization, and data analysis as a Device Engineer Intern.
Compensation
The hourly pay range for this position, which could be performed in the US, is $19.00 - $30.00.
Responsibilities
Support characterization and evaluation of semiconductor devices including MOSFETs, bipolar transistors, diodes, resistors, capacitors, and high-voltage devices.
Analyze silicon test data and identify trends related to device performance, variability, reliability, and process changes.
Develop scripts and automation tools using Python, MATLAB, JMP, or similar software to improve data analysis efficiency.
Assist in the design and execution of characterization experiments at wafer level and package level.
Support technology development activities including process transfers, technology benchmarking, and device optimization.
Requirements
Currently pursuing a degree in Electrical Engineering, Materials Science, Physics, Semiconductor Engineering, or a related technical field.
Nice to have: Coursework or project experience in semiconductor devices, microelectronics, IC fabrication, or solid-state physics
Nice to have: Experience with laboratory measurements and electronic test equipment
Nice to have: Familiarity with semiconductor characterization techniques and data analysis methods
Software Engineer focused on compiler development (Clang/LLVM/MLIR-based) for FPGA design tools, contributing to SoC design and verification workflows.
Compensation
The annual base salary range for this position is $76,000 - $114,000.*
Responsibilities
Develop, verify, and maintain advanced analysis and transformation passes for the state-of-the-art high-level synthesis (HLS) compiler.
Optimize HLS-generated hardware architectures to enhance power efficiency, performance, and area utilization.
Analyze complex, real-world customer applications created with high-level synthesis to identify opportunities for performance and area improvements.
Implement new HLS features as needed.
Requirements
Bachelor’s degree in Computer Science, Software Engineering, Computer Engineering, Electrical Engineering, or a related field
The Windows Engineering Manager is responsible for leading the engineering, delivery, and operational support of the enterprise Windows endpoint platform. This role provides technical and people leadership for a team of engineers responsible for the design, deployment, management, security, and lifecycle of end-user computing services across the organization.
Locations (2)
Reston, Virginia, United States
Plano, Texas, United States
Compensation
155,000.00 - 209,000.00
Responsibilities
Leading the engineering, delivery, and operational support of the enterprise Windows endpoint platform.
Driving the execution of the enterprise end-user computing strategy.
Overseeing engineering standards, operational processes, platform modernization initiatives, and service performance.
Leading a distributed team of approximately 8-10 desktop engineers and technicians.
Partnering with Infrastructure, Information Security, Network, and Enterprise Operations teams.
The successful candidate will participate in SoC DFT implementation, verification, and debug activities, supporting phases of SoC DFT-related activities including test insertion, pattern generation, coverage improvement, and silicon debug.
Compensation
The annual base salary range for this position is USD 68,800.00 To USD 110,000.00
Responsibilities
Assist with DFT implementation, including Scan, MBIST, TAP, and IO integration.
Support ATPG vector generation, simulation, and verification at the ASIC/Chip level.
Help debug test vectors before tape release and during ATE silicon bring-up.
Work closely with senior engineers on STA and design closure for test.
Automate DFT flows and scripts for improved engineering efficiency.
Requirements
Bachelor's degree in Electrical Engineering
Master's degree in Electrical Engineering
Bachelor's degree in Computer Engineering
Master's degree in Computer Engineering
Nice to have: Professional experience in DFT domain is a plus
The successful candidate will participate in SoC DFT implementation, verification, and debug activities including post-silicon bring up, supporting various phases of SoC DFT-related activities including test insertion, pattern generation, coverage improvement, and basic silicon debug.
Compensation
The annual base salary range for this position is USD 143,800.00 To USD 230,000.00.
Responsibilities
Understanding Broadcom & customer DFT feature requirements & DPPM goals & defining appropriate DFT specifications for the ASIC
Implementing DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes and other I/P DFT integration
Working closely with STA and DI Engineers design closure for test
Generating, Verifying & Debugging Test vectors before tape release
Validating & Debugging Test vectors on ATE during the silicon bring up phase
The anticipated starting base pay for this position is: $18.90 to $22.10 per hour
Responsibilities
Support construction projects to incorporate new field devices into current SCADA system
Work with graphical user interface to support transmission operations
Help with internal processes and documentation
Work with data analytics and be able to help with troubleshooting issues
Requirements
Current student, Sophomore or higher
Enrolled in an ABET accredited college or university and pursuing a degree in electrical engineering, computer science, computer information systems, management information systems, drafting, electric design
Lead Network Engineer responsible for designing, deploying, and managing enterprise-grade network infrastructure across retail stores and distribution centers.
Compensation
The pay range for this position is $128,500.00 - $164,000.00
Responsibilities
Lead end-to-end Aruba WiFi deployments for new and existing retail stores and distribution centers
Conduct professional RF site surveys using Ekahau Pro and similar tools
Design and maintain Aruba wireless infrastructure including APs, Mobility Conductors/Gateways, and AOS-8/AOS-10 architecture
Optimize RF environments for high-density retail and warehouse settings
Develop and enforce wireless security standards aligned with PCI-DSS requirements
Requirements
Bachelor's degree in Computer Science, Information Technology, Network Engineering, or equivalent
Nice to have: Aruba Certified Mobility Professional
Nice to have: Aruba Certified ClearPass Associate/Professional