Senior technical leader in DTCO to define and drive co-optimization of Intel Foundry's next-generation process technologies for analog, mixed-signal, and custom design.
Locations (2)
Hillsboro, Oregon, United States
Santa Clara, California, United States
Compensation
Annual Salary Range for jobs which could be performed in the US: $220,920.00-311,890.00 USD
Responsibilities
Lead AMS DTCO for future Intel Foundry nodes: evaluate device architecture, front-end and back-end design rules, metal stack, and patterning choices against analog, mixed-signal, and custom-design requirements.
Run a closed-loop DTCO process: sense issues from designers, partners, and test chips; prioritize by PPA and productivity impact; drive rule, PDK, or flow changes; and validate the result on silicon and in design.
Quantify technology impact on circuits through layout studies, parasitic-aware benchmarking, and area and performance scaling analysis of representative AMS building blocks.
Define and drive design-rule and PDK requirements with process, design-rule, OPC, and quality and reliability teams, including high-voltage device support, density and fill rules, metal width and spacing options, and layout-dependent effects.
Partner with EDA vendors on node enablement for custom and AMS flows: custom layout, analog placement and routing, physical verification, fill, and extraction; translate tool and flow feedback into technology decisions.
Development of high-speed and low-power Custom Circuit Designer (ex. Memory, FPGA Fabric Designer) implemented in advanced semiconductor technologies including FinFET and nanometer CMOS.
Responsibilities
Development of high-speed and low-power Custom Circuit Designer (ex. Memory, FPGA Fabric Designer).
Work involves schematic capture, SPICE simulations, and margin and functional verification of major circuit blocks.
Oversee layout planning and ensure tight pitch-matched memory layout and area optimized custom layout.
Work closely with architecture and design teams to define PPA (Performance, Power, Area) and yield targets.
Manage the full design flow, including circuit design, physical implementation, compiler usage, characterization, timing, and model generation.
Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM) using advanced semiconductor technologies.
Compensation
Base Pay Range 220800
Responsibilities
Lead the design and development of custom circuits for high-speed and low-power SRAM and low-power configuration RAM (CRAM)
Develop memory architectures and implement them in advanced semiconductor technologies, including FinFET and nanometer CMOS
Perform schematic capture, simulation, and margin verification of major memory blocks
Oversee layout planning and ensure tight pitch-matched memory layout designs
Work closely with architecture and design teams to define memory PPA (Performance, Power, Area) and yield targets
Requirements
Bachelor’s degree in electrical engineering, or a related field
Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface and delivery of our embedded memory compiler portfolio: single-port SRAM, ROM, single- and dual-port register files (1PRF, 2PRF), and dual-port RAM (DPRAM).
Responsibilities
Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM.
Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets.
Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects.
Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements.
Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification.
Design and develop high-speed IO circuits for next-generation memory interface PHY IPs including DDR, HBM, and UCIe in advanced CMOS, FinFET, and GAA process nodes.
Responsibilities
Design and develop high-speed IO circuits for next-generation memory interface PHY IPs
Execute circuit design tasks from architecture through layout, simulation, and verification with a focus on performance, power, and area optimization
Analyze and solve complex analog design challenges in advanced technology nodes
Collaborate with global cross-functional teams to deliver integrated PHY solutions
Apply ESD and reliability principles to ensure robust circuit design
Requirements
Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, or related field
Nice to have: knowledge of JEDEC memory interface standards (DDR, HBM, LPDDR)
Nice to have: familiarity with signal integrity and power integrity concepts
ASIC Analog Design Engineer on Micron’s ASIC design team, focused on supporting the AI and Virtuoso design environment, shaping ASICs used in Micron's tester and controller IP.
Compensation
$150,000.00 - $256,000.00 a year
Responsibilities
Be part of a highly skilled, high-speed PHY design team working on deep sub-micron technology nodes.
Flex between environment maintenance, flow development, and traditional schematic/layout designer roles as required by group needs.
Support enhancements and resolve bugs in the analog environment for both front-end and back-end tools and flows.
Maintain knowledge graph, graphRAG, or other information sources to improve effectiveness of AI agents.
Explore new ways of working to improve efficiency and quality of designs.
Staff Engineer to lead layout development for cutting-edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies, while mentoring juniors and collaborating with cross-functional teams.
Responsibilities
Lead layout development for cutting edge DDR, HBM, and UCIe PHY IP across 7nm and below process nodes including FinFET and GAA technologies
Own floorplanning, layout matching, ESD design, latch-up mitigation, and DFM compliance for analog and mixed-signal blocks
Drive layout reviews, quality checks, PERC and EMIR analysis, and release processes that meet both internal standards and customer requirements
Mentor junior layout engineers through hands-on technical leadership, teaching them how to solve real problems in deep submicron design
Collaborate with cross-functional teams including analog designers, verification engineers, and foundry partners to meet project timelines
Own critical custom datapath and matrix multiplication accumulator blocks, driving execution from RTL-to-GDSII including synthesis, floor-planning, place and route (PNR), timing closure, and physical signoff.
Understand math-intensive micro-architecture to perform detailed feasibility studies, analyzing performance, power, and area (PPA) tradeoffs to achieve optimal design closure.
Develop and improve advanced physical design methodologies and customize implementation recipes, specifically optimizing PPA across complex arithmetic pipeline structures.
The Analog Layout Engineer will design physical silicon layout for high-frequency or high-speed mixed-signal circuits using advanced CMOS/FinFET nodes like TSMC 4NM.
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