Responsible for digital implementation from synthesized netlist through final GDSII release, including floorplanning, power planning, place-and-route, clock-tree synthesis, timing closure, physical verification, power integrity analysis, and tapeout signoff.
Responsibilities
Drive block-level and full-chip physical design implementation from netlist to GDSII
Develop and execute floorplanning, power planning, placement, clock-tree synthesis (CTS), routing, and physical optimization flows
Own timing closure across multiple operating modes including functional, scan shift, and scan capture modes
Develop, optimize, and maintain CTS methodologies and scripts to support complex clock architectures and scan requirements
Perform static timing analysis (STA) and resolve setup, hold, clock skew, insertion delay, transition, and timing constraint violations
Requirements
BS, MS, or PhD in Electrical Engineering, Computer Engineering, or related field
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Technical leadership for ASIC development focusing on fullchip floorplan, RTL-to-GDSII implementation, and physical design.
Compensation
The starting salary range posted for this position is $147,400.00 to $198,200.00 and reflects the projected salary range for new hires in this position in U.S. and/or Canada locations, not including incentive compensation*, equity, or benefits.
Responsibilities
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning
Handson experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks
Silvaco is hiring a Memory Design Lead to drive the architecture, design, customer interface and delivery of our embedded memory compiler portfolio: single-port SRAM, ROM, single- and dual-port register files (1PRF, 2PRF), and dual-port RAM (DPRAM).
Responsibilities
Lead architecture, circuit design, and physical implementation of memory compilers across SRAM, ROM, 1-port and 2-port register files, and dual-port RAM.
Define bitcell selection, peripheral architecture (decoders, sense amps, write drivers, IO, self-timing), redundancy and repair strategy, and assist circuits (read/write assist, body bias) to hit aggressive PPA targets.
Drive Vmin, leakage, performance, area, and yield optimization across PVT corners, process variation, and aging effects.
Own the technical roadmap for the memory portfolio: new compiler variants, new nodes, feature enhancements, and methodology improvements.
Establish design, verification, and signoff methodology, while leading design and layout reviews, SPICE/FastSPICE characterization, statistical/Monte Carlo analysis, BIST/repair, DFT, and physical verification.
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing. Lead definition, design, verification, and/or documentation for ASIC development.
Responsibilities
Research, design, develop, and/or test electronic components and systems for semiconductor and related device manufacturing
Lead definition, design, verification, and/or documentation for ASIC development
Determine architecture design, logic design, and/or system simulation
Define module interfaces/formats for simulation
Lead the development of multidimensional designs involving the layout of complex integrated circuits
Develop chip package board PDN models and perform simulations to verify supply noise, impedance, and transient response; define PI requirements, specifications, and decoupling strategies; debug and root cause PI issues; correlate silicon measurements with simulations; collaborate with architecture, silicon, package, and board teams to deliver system aware PI solutions; improve PI methodologies, automation flows, and analysis processes.
Responsibilities
Develop chip package board PDN models and perform simulations to verify supply noise, impedance, and transient response
Define PI requirements, specifications, and decoupling strategies for all major power rails
Debug and root cause PI issues during bring up, validation, and production phases
Correlate silicon measurements with simulations and refine models accordingly
Collaborate with architecture, silicon, package, and board teams to deliver system aware PI solutions
Requirements
Bachelor's degree or foreign equivalent in Computer Engineering, Electrical Engineering, Electronic Engineering, or related field
The PDK team works with internal and external foundries to develop and deploy high-quality PDKs on both mature and advanced nodes. The role involves enhancing support for business units and taking over critical activities.
Responsibilities
Install/customize foundry PDKs and provide support for various product groups.
Develop, review, update and release foundry PDK and design methodologies for various business units.
Support circuit design and layout team with PDK related tasks such as design migrations, simulation, physical verification (DRC/LVS/ERC), EMIR, and parasitic extraction (PEX/QRC/StarRC).
Provide CAD support to designers in troubleshooting project setup, design environment configuration, tool integration, and day-to-day environment issues to ensure a stable and productive design flow.
Own technically complex PDK/CAD problems from investigation through resolution.
The Engineer will lead Broadcom's design methodology for 5nm and lower technology silicon, focusing on floor-planning, placement, CTS, route, and physical verification.
Responsibilities
Understanding of SoC for top-down/bottom-up physical design integration in 5nm and lower technologies
Maintain deep functional knowledge of P&R flows
Implement timing and functional ECO
P&R, Extraction, Physical verification, work towards STA closure
Build automation flows wherever needed/adapt to existing flows for re-use
Fullchip Floorplan by understanding the architecture of the design, foundry integration guidelines and IP placement constraints
Collaborate with the system and package design teams to understand the requirements and incorporate into the fullchip floorplan
Perform hierarchical implementation flow, including partition, pin assignment, clock plan and bump planning; Hands-on experience with Fullchip clock mesh and Flex-HTree methods
RTL-to-GDSII implementation: Floorplan, Power Grid plan, place and route, static timing analysis, power integrity, physical verification and equivalence checks with a focus on performance, power and die size optimization.
Analyze existing tool flows and methodologies, identifying efficiency gaps and implementing incremental or transformative enhancements.
ASIC Development Technical LeaderCisco · Vancouver, Canada+4 more
ASIC Development Technical LeaderCisco · Vancouver, Canada
SMTS Silicon Design EngineerAdvanced Micro Devices, Inc · San Diego, US
Physical Design EngineerApple · Cupertino, US