Referso Jobs

ASICS Design Engineer, Senior

Qualcomm · Posted Nov 9, 2026

Open

Hsinchu City, Taiwan
On-site
Senior
2–10 years

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ASICS Design Engineer, Senior

Qualcomm · Posted Nov 9, 2026

Open

Hsinchu City, Taiwan
On-site
Senior
2–10 years

Apply with Referso

ASICS Design Engineer, Staff

Qualcomm · Posted Nov 9, 2026

Open

Hsinchu City, Taiwan
On-site
Full-time · Staff
2–10 years

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Implement RTL design, synthesis, and timing closure for networking datapath/control logic for Ethernet switch ASICs.

Responsibilities

Implement RTL design, synthesis, and timing closure for networking datapath/control logic.
Participate in SoC integration with focus on Ethernet switch subsystems.
Lead design and delivery of key subsystems in Ethernet switch ASICs, driving architecture-aligned implementation and optimization.
Own micro-architecture and RTL design of networking blocks (e.g., forwarding engine, parser, traffic manager).
Drive subsystem integration, performance tuning, and power optimization.

Requirements

MS/BS in EE (MS preferred)
Bachelor's degree in Science, Engineering, or related field
Master's degree in Science, Engineering, or related field
PhD in Science, Engineering, or related field
Nice to have: merchant silicon

Skills

ASIC design logic design RTL coding verification synthesis

Sr. Staff RTL Eng

Lattice Semiconductor · Posted Aug 31, 2026

Open

Pune, Maharashtra, India
Senior
14+ years

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Senior Staff design engineer responsible for RTL development of machine learning engines on low‑power FPGA platforms.

Responsibilities

Develop and enhance RTL for machine learning engine
Implement ML operators efficiently on low‑power FPGA
Optimize data path for high throughput and low latency
Collaborate with algorithm and architecture teams to translate ML models into efficient hardware micro‑architectures
Design RTL for machine learning compute engines targeting low‑power FPGA platforms

Requirements

BE/MTech/PhD in Electronics, Electrical or Computer Engineering
Nice to have: Experience with C
Nice to have: Experience with SystemC

Skills

RTL design using Verilog RTL design using System Verilog-HDL Functional simulation using Xcelium Functional simulation using Cadence Functional simulation using VCS Functional simulation using Synopsys

Senior Design Engineer(FPGA RTL)

Lattice Semiconductor · Posted Sep 10, 2026

Open

Hyderabad, Telangana, India
Senior
5+ years

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Senior IP Design engineer with extensive FPGA RTL design experience

Responsibilities

Design FPGA RTL logic
Verify logic and perform timing closure
Debug hardware and validate designs
Package soft IP and develop testbenches

Requirements

BS/MS/PhD in Electronics or Computer Engineering
Nice to have: Hardware validation and debug
Nice to have: Soft IP packaging
Nice to have: Example design
Nice to have: Testbench development

Skills

FPGA RTL design Logic verification Debugging Timing closure C/C++Perl TCL Python High-speed IO protocols

Staff Applications Engineer

Lattice Semiconductor · Posted Jul 14, 2026

Open

Penang, Malaysia
Staff
10+ years

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Factory Applications Engineer supporting silicon design and customer enablement for low‑power programmable logic devices.

Responsibilities

Drive silicon feature enablement & improvement for a particular domain
Develop silicon enablement collaterals with focus on usability and performance
Develop and conduct trainings/workshops for sales & tech support team
Provide factory support and guidance to resolve customer issues
Collaborate closely with sales team to understand customer needs & solidify requirements to R&D

Requirements

BS/MS in Electrical Engineering

Skills

FPGA architecture PLL Embedded Memory blocks DSP blocks Input/Output blocks SSTL HSTL LVSTL

Sr Staff Design Engineer

Lattice Semiconductor · Posted May 13, 2026

Open

Pune, Maharashtra, India
Full-time · Senior
12+ years

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Responsibilities

Serve as a key contributor to FPGA design efforts
Drive physical design closure of key ASIC blocks & full chip and bring best-in-class methodologies to achieve best power, performance, and area
Ensuring design quality through all physical design quality checks and signoff
Develop strong relationships with worldwide teams
Mentor and develop strong partners and colleagues

Requirements

BS in Electronics Engineering
MS in Electronics Engineering
PhD in Electronics Engineering
BS in Electrical Engineering
MS in Electrical Engineering

Skills

RTL to GDSII flow place & route CTS routing floorplanning powerplanning timing physical signoff

Sr. Staff Design Engineer

Lattice Semiconductor · Posted Nov 3, 2026

Open

San Jose, California, United States
Senior
$219K–$219K per year
8+ years

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Responsible for RTL design and verification, leveraging deep expertise in Lattice Semiconductor products and customer applications across diverse market segments.

Compensation

Base Pay Range 218,889.00

Responsibilities

Developing complex systems from concept to board-level validation using Lattice proprietary FPGA architectures and tool flows.
Building embedded systems within Lattice FPGAs, including microprocessor design and embedded software development.
Integrating IPs into FPGA software flows and supporting end-to-end system implementation.
Analyzing hardware capabilities and contributing to customer solution strategies.
Architecting Soft IPs with detailed technical specifications and coordinating development efforts.

Requirements

Bachelor’s degree in Electronics Engineering, Applied Physics or related field

Skills

FPGA and SoC ASIC development IP for FPGA and ASIC products FPGA RTL design logic verification

Senior Soft IP Design Engineer

Lattice Semiconductor · Posted Nov 2, 2026

Open

Penang, Malaysia
Senior
7+ years

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Senior IP Design Engineer responsible for building Connectivity IP portfolios for Lattice FPGA, translating specifications into high-speed RTL design and ensuring performance, power, and logic utilization.

Responsibilities

Translate specifications into high-speed RTL design
Collaborate with architects to develop Connectivity IP portfolios
Ensure performance, power, and logic utilization
Perform verification, debug, and timing closure

Requirements

BS/MS/PhD in Electronics or Computer Engineering

Skills

high speed SERDES video protocols (DisplayPort, HDMI, MIPI, SDI)peripherals (SPI, I2C, I3C)FPGA RTL design CDC/lint verification debug timing closure

Engineer

Arrow Electronics, Inc. · Posted Apr 3, 2025

Open

Noida, Uttar Pradesh, India
Full-time · Associate
2–4 years

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The role involves working on floor-planning, timing constraints, physical synthesis, and block level place and route from Netlist through GDS flow.

Responsibilities

Work with teams on floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, signal integrity, physical verification and DFM.
Collaborate on executing the block level place and route assignments from Netlist through GDS flow.
Interact with design team with purpose to solve problems and propose physical design engineering ideas.
Coordinate all timing budgeting required for physical design task with respective teams.
Close STA timing across all corners and modes for blocks and should be able to generate ECO independently.

Requirements

4 year degree

Skills

floor-planning timing constraints physical synthesis formal verification clock tree optimization

Senior Engineer (Level 2)

Arrow Electronics, Inc. · Posted Jan 22, 2025

Open

Hyderabad, Telangana, India
Full-time · Senior
5–7 years

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Senior Engineer responsible for ASIC PNR flow, floor-planning, timing closure, and digital design automation.

Responsibilities

Responsible for floor-planning, timing constraints, physical synthesis, formal verification, clock tree optimization, routing, extraction, timing closure, DFT, antenna fixing & signal integrity, power grid analysis in ASIC PNR Flow
Execute block level place and route assignments from Netlist through GDS flow
Perform full chip implementation of complex SoCs (RTL-to-GDSII) if needed
Close STA timing across all corners and modes for blocks and generate ECO independently
Work with design teams for closing CTS, IO timing, DFT timing

Requirements

4 year degree
advanced degree

Skills

floor-planning timing constraints physical synthesis formal verification clock tree optimization routing

Timing Closure jobs

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